[{"additionalPlain":"Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.\nEqual Opportunity\nUpscale, Inc., is building a team that reflects a wide range of perspectives, backgrounds, and experiences. We’re proud to be an Equal Opportunity Employer and consider all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, disability, or veteran status.\nAccessibility & Accommodations\nWe’re committed to making our hiring process accessible to everyone. If you need accommodations at any stage, just reach out to us at hiring@upscaleai.com—we’re happy to help. Note: This inbox is only for accommodation requests.\n","additional":"

Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.

\n

Equal Opportunity

\n

Upscale, Inc., is building a team that reflects a wide range of perspectives, backgrounds, and experiences. We’re proud to be an Equal Opportunity Employer and consider all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, disability, or veteran status.

\n

Accessibility & Accommodations

\n

We’re committed to making our hiring process accessible to everyone. If you need accommodations at any stage, just reach out to us at hiring@upscaleai.com—we’re happy to help. Note: This inbox is only for accommodation requests.

","categories":{"commitment":"Reg - Full-Time","location":"US - Headquarters","team":"ASIC AI","allLocations":["US - Headquarters"]},"createdAt":1786667371160,"descriptionPlain":"Why join Upscale, Inc. \nUpscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.\nWe focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.\nIf you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. \n\n\nJob Responsibilities:\nAs a member of the ASIC Design team, you will work closely with the architecture team and define and document micro-architecture on next generation designs. \nResponsible for the logic design/RTL entry that meets the power, performance, area targets. \nCollaborate closely with design verification and emulation teams to confirm that test plans meet architecture and design intent, debug complex test scenarios and coverage closure\nWork closely with the physical design team on timing closure and area optimization \nWork with the design for test team to integrate DFT logic\nWork independently, communicate effectively and collaborate with cross functional teams \nRequirements:\nBE or MS in EE, CE, CS \n5+ years of related technical engineering experience.\n5+ years of industry experience in logic design on complex ASICs\nExperience with SystemVerilog for logic design\nUnderstanding of fundamental principles of logic design, clock domain crossing, synthesis and timing closure\nProficient communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams.\nAble to thrive or lead in a fast-paced startup environment.\nPreferred:\n12+ years of relevant industry experience with a proven track record of successful tapeouts \nScripting proficiency using Python, Perl etc. \nExperience with front end design tools like LINT, CDC, RDC\nExposure to silicon bring-up \nAnalyzing timing, area, power reports and ability to drive design fixes \nKnowledge of verification principles and coverage and ability to debug complex test cases\nBasic understanding of formal verification \nPast work experience on high performance, low latency networking ASICs is a big plus \nGrowth mindset and enthusiasm to learn and grow in a fast paced environment\n","description":"

Why join Upscale, Inc. 

\n

Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

\n

We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

\n

If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. 


\n

Job Responsibilities:

\n\n

Requirements:

\n\n

Preferred:

\n\n
","id":"368adbba-0271-4692-8113-66f74409d312","lists":[],"salaryRange":{"min":250000,"max":265000,"currency":"USD","interval":"per-year-salary"},"text":"ASIC Design - Principal Engineer","country":"US","workplaceType":"onsite","opening":"

Why join Upscale, Inc. 

\n

Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

\n

We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

\n

If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. 

","openingPlain":"Why join Upscale, Inc. \nUpscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.\nWe focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.\nIf you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. \n","descriptionBody":"
\n

Job Responsibilities:

\n\n

Requirements:

\n\n

Preferred:

\n\n
","descriptionBodyPlain":"Job Responsibilities:\nAs a member of the ASIC Design team, you will work closely with the architecture team and define and document micro-architecture on next generation designs. \nResponsible for the logic design/RTL entry that meets the power, performance, area targets. \nCollaborate closely with design verification and emulation teams to confirm that test plans meet architecture and design intent, debug complex test scenarios and coverage closure\nWork closely with the physical design team on timing closure and area optimization \nWork with the design for test team to integrate DFT logic\nWork independently, communicate effectively and collaborate with cross functional teams \nRequirements:\nBE or MS in EE, CE, CS \n5+ years of related technical engineering experience.\n5+ years of industry experience in logic design on complex ASICs\nExperience with SystemVerilog for logic design\nUnderstanding of fundamental principles of logic design, clock domain crossing, synthesis and timing closure\nProficient communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams.\nAble to thrive or lead in a fast-paced startup environment.\nPreferred:\n12+ years of relevant industry experience with a proven track record of successful tapeouts \nScripting proficiency using Python, Perl etc. \nExperience with front end design tools like LINT, CDC, RDC\nExposure to silicon bring-up \nAnalyzing timing, area, power reports and ability to drive design fixes \nKnowledge of verification principles and coverage and ability to debug complex test cases\nBasic understanding of formal verification \nPast work experience on high performance, low latency networking ASICs is a big plus \nGrowth mindset and enthusiasm to learn and grow in a fast paced environment\n","hostedUrl":"https://jobs.lever.co/upscale-ai/368adbba-0271-4692-8113-66f74409d312","applyUrl":"https://jobs.lever.co/upscale-ai/368adbba-0271-4692-8113-66f74409d312/apply"},{"additionalPlain":"Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.\nEqual Opportunity\nUpscale, Inc., is building a team that reflects a wide range of perspectives, backgrounds, and experiences. We’re proud to be an Equal Opportunity Employer and consider all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, disability, or veteran status.\nAccessibility & Accommodations\nWe’re committed to making our hiring process accessible to everyone. If you need accommodations at any stage, just reach out to us at hiring@upscaleai.com—we’re happy to help. Note: This inbox is only for accommodation requests.\n","additional":"

Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.

\n

Equal Opportunity

\n

Upscale, Inc., is building a team that reflects a wide range of perspectives, backgrounds, and experiences. We’re proud to be an Equal Opportunity Employer and consider all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, disability, or veteran status.

\n

Accessibility & Accommodations

\n

We’re committed to making our hiring process accessible to everyone. If you need accommodations at any stage, just reach out to us at hiring@upscaleai.com—we’re happy to help. Note: This inbox is only for accommodation requests.

","categories":{"commitment":"Reg - Full-Time","location":"US - Headquarters","team":"ASIC AI","allLocations":["US - Headquarters"]},"createdAt":1782944258841,"descriptionPlain":"Why join Upscale, Inc. \nUpscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.\nWe focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.\nIf you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. \n\n\nJob Responsibilities\nDesign, develop, and maintain robust verification environments, testbenches, reusable verification components, and reference models for block- and system-level designs.\nDevelop comprehensive verification plans and create test cases to ensure complete functional coverage.\nVerify RTL designs at both block and chip levels using directed testing, constrained-random verification, assertion-based verification (ABV), formal verification techniques, and functional coverage methodologies.\nPerform RTL code coverage analysis, assertion coverage, functional coverage, and gate-level simulations to validate design quality and completeness.\nDebug and resolve design and verification issues by collaborating closely with design, architecture, and cross-functional engineering teams.\nDrive the adoption of advanced verification methodologies, automation frameworks, and best practices to improve verification quality and efficiency.\nApply data-driven analytics and AI-assisted techniques to improve test generation, regression analysis, coverage optimization, and debug productivity.\nContinuously improve verification processes, infrastructure, and reusable verification IP to accelerate development cycles and enhance design quality and reliability.\n","description":"

Why join Upscale, Inc. 

\n

Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

\n

We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

\n

If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. 


\n

Job Responsibilities

\n\n
","id":"0d854ae0-1d8c-4261-ab23-8dc2b3d8b0e1","lists":[{"text":"Job Requirements","content":"

 

\n"}],"salaryRange":{"min":212000,"max":246000,"currency":"USD","interval":"per-year-salary"},"text":"Design Verification Engineer","country":"US","workplaceType":"onsite","opening":"

Why join Upscale, Inc. 

\n

Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

\n

We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

\n

If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. 

","openingPlain":"Why join Upscale, Inc. \nUpscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.\nWe focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.\nIf you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. \n","descriptionBody":"
\n

Job Responsibilities

\n\n
","descriptionBodyPlain":"Job Responsibilities\nDesign, develop, and maintain robust verification environments, testbenches, reusable verification components, and reference models for block- and system-level designs.\nDevelop comprehensive verification plans and create test cases to ensure complete functional coverage.\nVerify RTL designs at both block and chip levels using directed testing, constrained-random verification, assertion-based verification (ABV), formal verification techniques, and functional coverage methodologies.\nPerform RTL code coverage analysis, assertion coverage, functional coverage, and gate-level simulations to validate design quality and completeness.\nDebug and resolve design and verification issues by collaborating closely with design, architecture, and cross-functional engineering teams.\nDrive the adoption of advanced verification methodologies, automation frameworks, and best practices to improve verification quality and efficiency.\nApply data-driven analytics and AI-assisted techniques to improve test generation, regression analysis, coverage optimization, and debug productivity.\nContinuously improve verification processes, infrastructure, and reusable verification IP to accelerate development cycles and enhance design quality and reliability.\n","hostedUrl":"https://jobs.lever.co/upscale-ai/0d854ae0-1d8c-4261-ab23-8dc2b3d8b0e1","applyUrl":"https://jobs.lever.co/upscale-ai/0d854ae0-1d8c-4261-ab23-8dc2b3d8b0e1/apply"},{"additionalPlain":"Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.\nEqual Opportunity\nUpscale, Inc., is building a team that reflects a wide range of perspectives, backgrounds, and experiences. We’re proud to be an Equal Opportunity Employer and consider all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, disability, or veteran status.\nAccessibility & Accommodations\nWe’re committed to making our hiring process accessible to everyone. If you need accommodations at any stage, just reach out to us at hiring@upscaleai.com—we’re happy to help. Note: This inbox is only for accommodation requests.\n","additional":"

Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.

\n

Equal Opportunity

\n

Upscale, Inc., is building a team that reflects a wide range of perspectives, backgrounds, and experiences. We’re proud to be an Equal Opportunity Employer and consider all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, disability, or veteran status.

\n

Accessibility & Accommodations

\n

We’re committed to making our hiring process accessible to everyone. If you need accommodations at any stage, just reach out to us at hiring@upscaleai.com—we’re happy to help. Note: This inbox is only for accommodation requests.

","categories":{"commitment":"Reg - Full-Time","location":"India - Bangalore","team":"Product Support","allLocations":["India - Bangalore"]},"createdAt":1781409292294,"descriptionPlain":"Why join Upscale, Inc. \nUpscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.\nWe focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.\nIf you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. \n\n\nUpscale is building the engineering team that drives product improvements though hands-on field engineering. The Forward-Deployed Engineer (FDE) owns complex fabric and system issues end-to-end: from first report through root-cause analysis, workaround delivery, and verified fix. You resolve them with the rest of the team, or you drive them to resolution across whatever boundary stands in the way. \nThis role is new to UpscaleAI and sits at the intersection of support, engineering, and product management. You will work directly with customers running production AI fabrics, reproduce issues in the lab, develop workarounds under pressure, and contribute fixes and diagnostic content back into the product and our AI-driven monitoring agent. \nThe environment is often unstructured. Problem definitions are incomplete. Documentation may not exist yet. The right candidate sees that as an opportunity, not an obstacle. \nLarge AI infrastructure operators increasingly expect their vendor's engineering team to function as an extension of their own infrastructure organization. This role is built to meet that expectation. \nThis is a small team. There will be an on-call component, but we are building a global team to reduce out-of-hours calls. We work with customers directly, so some travel is involved. Remote meeting tools handle much of the collaboration but building strong trust relationships will require time on site. \n","description":"

Why join Upscale, Inc. 

\n

Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

\n

We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

\n

If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. 


\n
\n

Upscale is building the engineering team that drives product improvements though hands-on field engineering. The Forward-Deployed Engineer (FDE) owns complex fabric and system issues end-to-end: from first report through root-cause analysis, workaround delivery, and verified fix. You resolve them with the rest of the team, or you drive them to resolution across whatever boundary stands in the way. 

\n
\n
\n

This role is new to UpscaleAI and sits at the intersection of support, engineering, and product management. You will work directly with customers running production AI fabrics, reproduce issues in the lab, develop workarounds under pressure, and contribute fixes and diagnostic content back into the product and our AI-driven monitoring agent. 

\n
\n
\n

The environment is often unstructured. Problem definitions are incomplete. Documentation may not exist yet. The right candidate sees that as an opportunity, not an obstacle. 

\n
\n
\n

Large AI infrastructure operators increasingly expect their vendor's engineering team to function as an extension of their own infrastructure organization. This role is built to meet that expectation. 

\n
\n
\n

This is a small team. There will be an on-call component, but we are building a global team to reduce out-of-hours calls. We work with customers directly, so some travel is involved. Remote meeting tools handle much of the collaboration but building strong trust relationships will require time on site. 

\n
\n
","id":"d86b9479-5716-4903-a2f4-ab3dd93ff8b3","lists":[{"text":"Key Responsibilities ","content":"
\n
\n
\n
    \n
  • \n

    Triage and resolve complex AI fabric issues: including silent packet drops, queue anomalies, NCCL stalls, gray failures, and performance degradation in production environments. You own the problem from intake to resolution. 

    \n
  • \n\n
\n
\n
    \n
  • \n

    Reproduce issues in the lab: building test scenarios that isolate L2 and L3 problems (packet loss, latency, retransmits, ECMP behavior, PFC/ECN interactions) and deliver reproducible cases to the development team when code fixes are needed. 

    \n
  • \n\n
\n
\n
\n
\n
    \n
  • \n

    Act as the escalation buffer for engineering: resolving issues without engaging development when possible, and packaging clean, reproducible problem statements when development engagement is required. 

    \n
  • \n\n
\n
\n
    \n
  • \n

    Train and improve the on-box and off-box AI agents: contributing field-validated detection signatures, classification logic, and resolution recommendations based on real cases. Your field experience directly shapes what the agent can identify and handle autonomously. 

    \n
  • \n\n
\n
\n
    \n
  • \n

    Validate AI agent accuracy: reviewing the agent's data collection, anomaly detection, and triage classifications against real-world outcomes. You determine when the agent is ready to advance from data collection to active triage to mitigation 

    \n
  • \n\n
\n
\n
    \n
  • \n

    Work with customers directly: understanding their fabric topology, workload patterns, and operational constraints. Communicate findings clearly to both technical and non-technical stakeholders. 

    \n
  • \n\n
\n
\n
    \n
  • \n

    Contribute to the product: identifying supportability gaps, proposing diagnostic improvements, and feeding field insights into the product management process. You are an active voice in what the product needs to become. 

    \n
  • \n\n
\n
\n
    \n
  • \n

    Maintain and evolve the AI agent's detection capabilities: update detection signatures, retrain classification models, and tune thresholds as customer fabrics scale, new hardware is deployed, and new failure modes are discovered in the field. The AI agent is an evolving system, not a shipped product. 

    \n
  • \n\n
\n
\n
    \n
  • \n

    Read and work with source code: engaging with developers at the code level when needed to understand behavior, identify root causes, or validate fixes. You do not need to be a full-time developer, but you must be comfortable in the codebase. 

    \n
  • \n\n
\n
\n


Requirements
 

\n
\n
\n

5+ years of hands-on experience with high speed data center switching platforms at scale. Experience with AI fabric deployments is a strong plus but not required if switching and troubleshooting background depth is there. 

\n
\n
\n

People who take ownership. The FDE role requires someone who treats every problem as theirs until it's resolved, regardless of where the root cause sits. If the issue crosses into ASIC behavior, NOS code, optics firmware, or customer configuration, you follow it there. Pointing to another team is not a resolution. 

\n
\n
\n
    \n
  • \n

    Deep Ethernet troubleshooting experience, including L2/L3 forwarding, ECMP, and packet-level analysis 

    \n
  • \n\n
\n
\n
    \n
  • \n

    BGP operations experience, including route reflectors, convergence behavior, and fabric-scale deployments 

    \n
  • \n\n
\n
\n
    \n
  • \n

    QoS configuration and troubleshooting: PFC, ECN, DSCP, queue management 

    \n
  • \n\n
\n
\n
    \n
  • \n

    Hardware support background: ASICs, FPGAs, chassis-based platforms, pluggable optic modules 

    \n
  • \n\n
\n
\n
    \n
  • \n

    Fiber and optical link troubleshooting, including DOM telemetry interpretation 

    \n
  • \n\n
\n
\n
    \n
  • \n

    Software support history: working with NOS, firmware, and driver-level issues 

    \n
  • \n\n
\n
\n
    \n
  • \n

    Linux proficiency (command line, system administration, log analysis) 

    \n
  • \n\n
\n
\n
    \n
  • \n

    Telemetry and monitoring: experience with streaming telemetry, counters, and event-driven diagnostics 

    \n
  • \n\n
\n
\n
    \n
  • \n

    Experience contributing to or training ML/AI systems (classification models, labeled data, feedback loops) 

    \n
  • \n\n
\n
\n
    \n
  • \n

    Lab skills: ability to design, build, and execute complex test scenarios that isolate specific failure modes 

    \n
  • \n\n
\n
\n
\n
\n
    \n
  • \n

    Clear written and verbal communication, including customer-facing interaction 

    \n
  • \n\n
\n
\n

Nice to have 

\n
\n
\n
    \n
  • \n

    Experience with SONiC or other open network operating systems 

    \n
  • \n\n
\n
\n
    \n
  • \n

    Familiarity with AI data center designs: low-latency fabrics, GPU cluster networking, NCCL, RDMA/RoCEv2 

    \n
  • \n\n
\n
\n
    \n
  • \n

    Experience with NVIDIA Spectrum switch family, BlueField SuperNICs, or ConnectX adapters 

    \n
  • \n\n
\n
\n
    \n
  • \n

    Understanding of Ultra Ethernet Consortium specifications and goals 

    \n
  • \n\n
\n
\n
    \n
  • \n

    PCIe architecture knowledge (relevant to NIC and accelerator integration) 

    \n
  • \n\n
\n
\n
    \n
  • \n

    Experience with Ixia/Keysight or similar network test equipment and test suites 

    \n
  • \n\n
\n
\n
    \n
  • \n

    Exposure to high-frequency telemetry (HFT) or WJH (What Just Happened) event data 

    \n
  • \n\n
\n
\n

What This Role Is Not 

\n
\n
\n

This is not a traditional TAC or support queue role. You will not be working from runbooks or following scripts. Many of the problems you encounter will not have documented solutions. You will be expected to figure it out, document it, and make sure the next engineer (or the agent) can handle it, next time, without you. 

\n
\n
\n

This is also not a development role. You will read code and work closely with developers, but your primary output is resolved customer issues, validated agent training data, and product improvement recommendations, not shipped features. 

\n
\n
\n
"}],"text":"Forward-Deployed Engineer, AI Fabric","country":"IN","workplaceType":"onsite","opening":"

Why join Upscale, Inc. 

\n

Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

\n

We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

\n

If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. 

","openingPlain":"Why join Upscale, Inc. \nUpscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.\nWe focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.\nIf you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. \n","descriptionBody":"
\n
\n

Upscale is building the engineering team that drives product improvements though hands-on field engineering. The Forward-Deployed Engineer (FDE) owns complex fabric and system issues end-to-end: from first report through root-cause analysis, workaround delivery, and verified fix. You resolve them with the rest of the team, or you drive them to resolution across whatever boundary stands in the way. 

\n
\n
\n

This role is new to UpscaleAI and sits at the intersection of support, engineering, and product management. You will work directly with customers running production AI fabrics, reproduce issues in the lab, develop workarounds under pressure, and contribute fixes and diagnostic content back into the product and our AI-driven monitoring agent. 

\n
\n
\n

The environment is often unstructured. Problem definitions are incomplete. Documentation may not exist yet. The right candidate sees that as an opportunity, not an obstacle. 

\n
\n
\n

Large AI infrastructure operators increasingly expect their vendor's engineering team to function as an extension of their own infrastructure organization. This role is built to meet that expectation. 

\n
\n
\n

This is a small team. There will be an on-call component, but we are building a global team to reduce out-of-hours calls. We work with customers directly, so some travel is involved. Remote meeting tools handle much of the collaboration but building strong trust relationships will require time on site. 

\n
\n
","descriptionBodyPlain":"Upscale is building the engineering team that drives product improvements though hands-on field engineering. The Forward-Deployed Engineer (FDE) owns complex fabric and system issues end-to-end: from first report through root-cause analysis, workaround delivery, and verified fix. You resolve them with the rest of the team, or you drive them to resolution across whatever boundary stands in the way. \nThis role is new to UpscaleAI and sits at the intersection of support, engineering, and product management. You will work directly with customers running production AI fabrics, reproduce issues in the lab, develop workarounds under pressure, and contribute fixes and diagnostic content back into the product and our AI-driven monitoring agent. \nThe environment is often unstructured. Problem definitions are incomplete. Documentation may not exist yet. The right candidate sees that as an opportunity, not an obstacle. \nLarge AI infrastructure operators increasingly expect their vendor's engineering team to function as an extension of their own infrastructure organization. This role is built to meet that expectation. \nThis is a small team. There will be an on-call component, but we are building a global team to reduce out-of-hours calls. We work with customers directly, so some travel is involved. Remote meeting tools handle much of the collaboration but building strong trust relationships will require time on site. \n","hostedUrl":"https://jobs.lever.co/upscale-ai/d86b9479-5716-4903-a2f4-ab3dd93ff8b3","applyUrl":"https://jobs.lever.co/upscale-ai/d86b9479-5716-4903-a2f4-ab3dd93ff8b3/apply"},{"additionalPlain":"Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.\nEqual Opportunity\nUpscale, Inc., is building a team that reflects a wide range of perspectives, backgrounds, and experiences. We’re proud to be an Equal Opportunity Employer and consider all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, disability, or veteran status.\nAccessibility & Accommodations\nWe’re committed to making our hiring process accessible to everyone. If you need accommodations at any stage, just reach out to us at hiring@upscaleai.com—we’re happy to help. Note: This inbox is only for accommodation requests.\n","additional":"

Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.

\n

Equal Opportunity

\n

Upscale, Inc., is building a team that reflects a wide range of perspectives, backgrounds, and experiences. We’re proud to be an Equal Opportunity Employer and consider all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, disability, or veteran status.

\n

Accessibility & Accommodations

\n

We’re committed to making our hiring process accessible to everyone. If you need accommodations at any stage, just reach out to us at hiring@upscaleai.com—we’re happy to help. Note: This inbox is only for accommodation requests.

","categories":{"commitment":"Reg - Full-Time","location":"India - Bangalore","team":"AI Network Software","allLocations":["India - Bangalore"]},"createdAt":1783950182311,"descriptionPlain":"Why join Upscale, Inc. \nUpscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.\nWe focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.\nIf you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. \n\n\nWe are seeking a highly skilled gNMI Engineer with strong expertise in SONiC (Software for Open Networking in the Cloud), network programmability, telemetry, and automation. The ideal candidate will be responsible for designing, developing, integrating, and maintaining gNMI-based management and telemetry solutions for SONiC-enabled network devices. The role requires deep understanding of YANG models, OpenConfig, gRPC/gNMI protocols, and modern datacentre networking technologies.\n \nThe engineer will work closely with SONiC developers, network architects, automation teams, and cloud infrastructure teams to build scalable network management and observability solutions.\n \nWhat will you do ?\n• Design and implement gNMI-based configuration and telemetry solutions for SONiC switches. Maintain gNMI clients, servers, and related services.\n• Integrate SONiC management interfaces with OpenConfig and vendor-specific YANG models.\n• Enhance manageability solutions using gNMI Subscribe, Get, Set, and Capabilities operations. Implement streaming telemetry solutions using: gNMI and OpenConfig\n• Support integration of SONiC with data center orchestration platforms.\n• Troubleshoot and optimize gRPC/gNMI communication for large-scale deployments.\n• Contribute to SONiC management framework enhancements.\n• Develop automation frameworks using: Python, Go (Golang)\n• Debug protocol-level issues involving: gRPC, gNMI, OpenConfig, YANG, perform packet captures and protocol analysis.\n• Resolve scalability and performance issues in telemetry systems. Conduct root cause analysis and provide long-term solutions.\n• Contribute to SONiC Community.\n \nWho you are?\n \nMust Have Skills:\n• Engineering background with 15+ years of software development experience\n• Strong experience with: SONiC, gNMI, gRPC, OpenConfig, Yang Data Models\n• Hands-on experience in: Python, Go (Golang)\n• Solid understanding of: Linux system commands, Container technologies (Docker)\n• Experience with: NETCONF, gNOI, OpenTelemetry\n• Deep understanding of Networking, Switching platforms, TCP/IP, BGP, EVPN-VXLAN, Data Centre Networking\n• Strong analytical and problem-solving skills, excellent debugging and troubleshooting abilities.\n• Ability to work in Agile development environments.\n• Self-driven with ownership mindset. Strong communication and cross-functional collaboration skills.\n \nGood to have\n• Contributions to SONiC open-source community.\n• Familiarity with SONiC Management Framework.\n• Experience with hyperscale datacenter environments.\n","description":"

Why join Upscale, Inc. 

\n

Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

\n

We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

\n

If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. 


\n
We are seeking a highly skilled gNMI Engineer with strong expertise in SONiC (Software for Open Networking in the Cloud), network programmability, telemetry, and automation. The ideal candidate will be responsible for designing, developing, integrating, and maintaining gNMI-based management and telemetry solutions for SONiC-enabled network devices. The role requires deep understanding of YANG models, OpenConfig, gRPC/gNMI protocols, and modern datacentre networking technologies.
\n
 
\n
The engineer will work closely with SONiC developers, network architects, automation teams, and cloud infrastructure teams to build scalable network management and observability solutions.
\n
 
\n
What will you do ?
\n
• Design and implement gNMI-based configuration and telemetry solutions for SONiC switches. Maintain gNMI clients, servers, and related services.
\n
• Integrate SONiC management interfaces with OpenConfig and vendor-specific YANG models.
\n
• Enhance manageability solutions using gNMI Subscribe, Get, Set, and Capabilities operations. Implement streaming telemetry solutions using: gNMI and OpenConfig
\n
• Support integration of SONiC with data center orchestration platforms.
\n
• Troubleshoot and optimize gRPC/gNMI communication for large-scale deployments.
\n
• Contribute to SONiC management framework enhancements.
\n
• Develop automation frameworks using: Python, Go (Golang)
\n
• Debug protocol-level issues involving: gRPC, gNMI, OpenConfig, YANG, perform packet captures and protocol analysis.
\n
• Resolve scalability and performance issues in telemetry systems. Conduct root cause analysis and provide long-term solutions.
\n
• Contribute to SONiC Community.
\n
 
\n
Who you are?
\n
 
\n
Must Have Skills:
\n
• Engineering background with 15+ years of software development experience
\n
• Strong experience with: SONiC, gNMI, gRPC, OpenConfig, Yang Data Models
\n
• Hands-on experience in: Python, Go (Golang)
\n
• Solid understanding of: Linux system commands, Container technologies (Docker)
\n
• Experience with: NETCONF, gNOI, OpenTelemetry
\n
• Deep understanding of Networking, Switching platforms, TCP/IP, BGP, EVPN-VXLAN, Data Centre Networking
\n
• Strong analytical and problem-solving skills, excellent debugging and troubleshooting abilities.
\n
• Ability to work in Agile development environments.
\n
• Self-driven with ownership mindset. Strong communication and cross-functional collaboration skills.
\n
 
\n
Good to have
\n
• Contributions to SONiC open-source community.
\n
• Familiarity with SONiC Management Framework.
\n
• Experience with hyperscale datacenter environments.
\n
","id":"749a5df9-9f1c-4590-b162-7531b5b8ed10","lists":[],"text":"Principal Engineer - SONiC Manageability & Telemetry","country":"IN","workplaceType":"onsite","opening":"

Why join Upscale, Inc. 

\n

Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

\n

We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

\n

If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. 

","openingPlain":"Why join Upscale, Inc. \nUpscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.\nWe focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.\nIf you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. \n","descriptionBody":"
\n
We are seeking a highly skilled gNMI Engineer with strong expertise in SONiC (Software for Open Networking in the Cloud), network programmability, telemetry, and automation. The ideal candidate will be responsible for designing, developing, integrating, and maintaining gNMI-based management and telemetry solutions for SONiC-enabled network devices. The role requires deep understanding of YANG models, OpenConfig, gRPC/gNMI protocols, and modern datacentre networking technologies.
\n
 
\n
The engineer will work closely with SONiC developers, network architects, automation teams, and cloud infrastructure teams to build scalable network management and observability solutions.
\n
 
\n
What will you do ?
\n
• Design and implement gNMI-based configuration and telemetry solutions for SONiC switches. Maintain gNMI clients, servers, and related services.
\n
• Integrate SONiC management interfaces with OpenConfig and vendor-specific YANG models.
\n
• Enhance manageability solutions using gNMI Subscribe, Get, Set, and Capabilities operations. Implement streaming telemetry solutions using: gNMI and OpenConfig
\n
• Support integration of SONiC with data center orchestration platforms.
\n
• Troubleshoot and optimize gRPC/gNMI communication for large-scale deployments.
\n
• Contribute to SONiC management framework enhancements.
\n
• Develop automation frameworks using: Python, Go (Golang)
\n
• Debug protocol-level issues involving: gRPC, gNMI, OpenConfig, YANG, perform packet captures and protocol analysis.
\n
• Resolve scalability and performance issues in telemetry systems. Conduct root cause analysis and provide long-term solutions.
\n
• Contribute to SONiC Community.
\n
 
\n
Who you are?
\n
 
\n
Must Have Skills:
\n
• Engineering background with 15+ years of software development experience
\n
• Strong experience with: SONiC, gNMI, gRPC, OpenConfig, Yang Data Models
\n
• Hands-on experience in: Python, Go (Golang)
\n
• Solid understanding of: Linux system commands, Container technologies (Docker)
\n
• Experience with: NETCONF, gNOI, OpenTelemetry
\n
• Deep understanding of Networking, Switching platforms, TCP/IP, BGP, EVPN-VXLAN, Data Centre Networking
\n
• Strong analytical and problem-solving skills, excellent debugging and troubleshooting abilities.
\n
• Ability to work in Agile development environments.
\n
• Self-driven with ownership mindset. Strong communication and cross-functional collaboration skills.
\n
 
\n
Good to have
\n
• Contributions to SONiC open-source community.
\n
• Familiarity with SONiC Management Framework.
\n
• Experience with hyperscale datacenter environments.
\n
","descriptionBodyPlain":"We are seeking a highly skilled gNMI Engineer with strong expertise in SONiC (Software for Open Networking in the Cloud), network programmability, telemetry, and automation. The ideal candidate will be responsible for designing, developing, integrating, and maintaining gNMI-based management and telemetry solutions for SONiC-enabled network devices. The role requires deep understanding of YANG models, OpenConfig, gRPC/gNMI protocols, and modern datacentre networking technologies.\n \nThe engineer will work closely with SONiC developers, network architects, automation teams, and cloud infrastructure teams to build scalable network management and observability solutions.\n \nWhat will you do ?\n• Design and implement gNMI-based configuration and telemetry solutions for SONiC switches. Maintain gNMI clients, servers, and related services.\n• Integrate SONiC management interfaces with OpenConfig and vendor-specific YANG models.\n• Enhance manageability solutions using gNMI Subscribe, Get, Set, and Capabilities operations. Implement streaming telemetry solutions using: gNMI and OpenConfig\n• Support integration of SONiC with data center orchestration platforms.\n• Troubleshoot and optimize gRPC/gNMI communication for large-scale deployments.\n• Contribute to SONiC management framework enhancements.\n• Develop automation frameworks using: Python, Go (Golang)\n• Debug protocol-level issues involving: gRPC, gNMI, OpenConfig, YANG, perform packet captures and protocol analysis.\n• Resolve scalability and performance issues in telemetry systems. Conduct root cause analysis and provide long-term solutions.\n• Contribute to SONiC Community.\n \nWho you are?\n \nMust Have Skills:\n• Engineering background with 15+ years of software development experience\n• Strong experience with: SONiC, gNMI, gRPC, OpenConfig, Yang Data Models\n• Hands-on experience in: Python, Go (Golang)\n• Solid understanding of: Linux system commands, Container technologies (Docker)\n• Experience with: NETCONF, gNOI, OpenTelemetry\n• Deep understanding of Networking, Switching platforms, TCP/IP, BGP, EVPN-VXLAN, Data Centre Networking\n• Strong analytical and problem-solving skills, excellent debugging and troubleshooting abilities.\n• Ability to work in Agile development environments.\n• Self-driven with ownership mindset. Strong communication and cross-functional collaboration skills.\n \nGood to have\n• Contributions to SONiC open-source community.\n• Familiarity with SONiC Management Framework.\n• Experience with hyperscale datacenter environments.\n","hostedUrl":"https://jobs.lever.co/upscale-ai/749a5df9-9f1c-4590-b162-7531b5b8ed10","applyUrl":"https://jobs.lever.co/upscale-ai/749a5df9-9f1c-4590-b162-7531b5b8ed10/apply"},{"additionalPlain":"Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.\nEqual Opportunity\nUpscale, Inc., is building a team that reflects a wide range of perspectives, backgrounds, and experiences. We’re proud to be an Equal Opportunity Employer and consider all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, disability, or veteran status.\nAccessibility & Accommodations\nWe’re committed to making our hiring process accessible to everyone. If you need accommodations at any stage, just reach out to us at hiring@upscaleai.com—we’re happy to help. Note: This inbox is only for accommodation requests.\n","additional":"

Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.

\n

Equal Opportunity

\n

Upscale, Inc., is building a team that reflects a wide range of perspectives, backgrounds, and experiences. We’re proud to be an Equal Opportunity Employer and consider all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, disability, or veteran status.

\n

Accessibility & Accommodations

\n

We’re committed to making our hiring process accessible to everyone. If you need accommodations at any stage, just reach out to us at hiring@upscaleai.com—we’re happy to help. Note: This inbox is only for accommodation requests.

","categories":{"commitment":"Reg - Full-Time","location":"India - Bangalore","team":"ASIC AI","allLocations":["India - Bangalore"]},"createdAt":1784014118218,"descriptionPlain":"Why join Upscale, Inc. \nUpscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.\nWe focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.\nIf you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. \n\n\nWe are looking for a highly technical, hands-on Principal DV Engineer to anchor the verification of our next-generation, high-performance networking silicon. In this role, you will be the primary technical driver for complex IPs and critical sub-systems. You will balance advanced architectural environment creation with rigorous execution, leading by example on the engineering floor. This position is ideal for a veteran engineer who loves breaking complex designs, building elite UVM environments, and mentoring the next generation of verification talent.\nKey Responsibilities\nIP & Sub-system Leadership: Own the complete verification lifecycle for critical high-performance networking IPs and large-scale sub-systems.\nUVM Environment Architecture: Architect, develop, and maintain advanced, scalable constrained-random verification environments from scratch using System Verilog and UVM.\nTest Planning & Execution: Author comprehensive, bulletproof verification plans. Drive test case development, regressions, triage, and coverage closure (functional, code, and assertion-based metrics).\nAdvanced Debugging: Serve as the team's go-to expert for isolating and resolving the most complex, deep-seated hardware bugs.\nLead by Example: Actively participate in design and verification code reviews. Maintain high standards of code quality, reuse, and documentation within the execution team.\nCross-Functional Alignment: Partner closely with Design and Architecture teams to resolve ambiguities early in the design cycle and ensure high-quality delivery.\nRequired Qualifications & Skills\nExperience: 15+ years of solid experience in ASIC/SoC Design Verification with a proven track record of successful tape-outs.\nDomain Expertise: Extensive experience in the networking domain, verifying high-throughput, data-intensive designs.\nMethodology Expert: Mastery of System Verilog and UVM. Must have a proven history of writing complex testbenches and VIP integrations from scratch.\nVerification Scope: Proven experience leading verification at the IP and Sub-system level, with strong exposure to SoC integration.\nEducation: B Tech/M Tech in Electronics/Electrical Engineering, Computer Engineering, or a related field.\nPreferred / Added Advantages\nHands-on experience with Formal Property Verification (FPV) to exhaustively verify block-level control logic.\nProficiency in Python or Perl for testbench automation and triage scripting.\n","description":"

Why join Upscale, Inc. 

\n

Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

\n

We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

\n

If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. 


\n
We are looking for a highly technical, hands-on Principal DV Engineer to anchor the verification of our next-generation, high-performance networking silicon. In this role, you will be the primary technical driver for complex IPs and critical sub-systems. You will balance advanced architectural environment creation with rigorous execution, leading by example on the engineering floor. This position is ideal for a veteran engineer who loves breaking complex designs, building elite UVM environments, and mentoring the next generation of verification talent.
\n
Key Responsibilities
\n\n
Required Qualifications & Skills
\n\n
Preferred / Added Advantages
\n\n
","id":"33b1a9d4-483b-4f9b-b2cb-9e7bcd2994f6","lists":[],"text":"Principal Engineer – Design Verification","country":"IN","workplaceType":"onsite","opening":"

Why join Upscale, Inc. 

\n

Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

\n

We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

\n

If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. 

","openingPlain":"Why join Upscale, Inc. \nUpscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.\nWe focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.\nIf you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. \n","descriptionBody":"
\n
We are looking for a highly technical, hands-on Principal DV Engineer to anchor the verification of our next-generation, high-performance networking silicon. In this role, you will be the primary technical driver for complex IPs and critical sub-systems. You will balance advanced architectural environment creation with rigorous execution, leading by example on the engineering floor. This position is ideal for a veteran engineer who loves breaking complex designs, building elite UVM environments, and mentoring the next generation of verification talent.
\n
Key Responsibilities
\n\n
Required Qualifications & Skills
\n\n
Preferred / Added Advantages
\n\n
","descriptionBodyPlain":"We are looking for a highly technical, hands-on Principal DV Engineer to anchor the verification of our next-generation, high-performance networking silicon. In this role, you will be the primary technical driver for complex IPs and critical sub-systems. You will balance advanced architectural environment creation with rigorous execution, leading by example on the engineering floor. This position is ideal for a veteran engineer who loves breaking complex designs, building elite UVM environments, and mentoring the next generation of verification talent.\nKey Responsibilities\nIP & Sub-system Leadership: Own the complete verification lifecycle for critical high-performance networking IPs and large-scale sub-systems.\nUVM Environment Architecture: Architect, develop, and maintain advanced, scalable constrained-random verification environments from scratch using System Verilog and UVM.\nTest Planning & Execution: Author comprehensive, bulletproof verification plans. Drive test case development, regressions, triage, and coverage closure (functional, code, and assertion-based metrics).\nAdvanced Debugging: Serve as the team's go-to expert for isolating and resolving the most complex, deep-seated hardware bugs.\nLead by Example: Actively participate in design and verification code reviews. Maintain high standards of code quality, reuse, and documentation within the execution team.\nCross-Functional Alignment: Partner closely with Design and Architecture teams to resolve ambiguities early in the design cycle and ensure high-quality delivery.\nRequired Qualifications & Skills\nExperience: 15+ years of solid experience in ASIC/SoC Design Verification with a proven track record of successful tape-outs.\nDomain Expertise: Extensive experience in the networking domain, verifying high-throughput, data-intensive designs.\nMethodology Expert: Mastery of System Verilog and UVM. Must have a proven history of writing complex testbenches and VIP integrations from scratch.\nVerification Scope: Proven experience leading verification at the IP and Sub-system level, with strong exposure to SoC integration.\nEducation: B Tech/M Tech in Electronics/Electrical Engineering, Computer Engineering, or a related field.\nPreferred / Added Advantages\nHands-on experience with Formal Property Verification (FPV) to exhaustively verify block-level control logic.\nProficiency in Python or Perl for testbench automation and triage scripting.\n","hostedUrl":"https://jobs.lever.co/upscale-ai/33b1a9d4-483b-4f9b-b2cb-9e7bcd2994f6","applyUrl":"https://jobs.lever.co/upscale-ai/33b1a9d4-483b-4f9b-b2cb-9e7bcd2994f6/apply"},{"additionalPlain":"Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.\nEqual Opportunity\nUpscale, Inc., is building a team that reflects a wide range of perspectives, backgrounds, and experiences. We’re proud to be an Equal Opportunity Employer and consider all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, disability, or veteran status.\nAccessibility & Accommodations\nWe’re committed to making our hiring process accessible to everyone. If you need accommodations at any stage, just reach out to us at hiring@upscaleai.com—we’re happy to help. Note: This inbox is only for accommodation requests.\n","additional":"

Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.

\n

Equal Opportunity

\n

Upscale, Inc., is building a team that reflects a wide range of perspectives, backgrounds, and experiences. We’re proud to be an Equal Opportunity Employer and consider all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, disability, or veteran status.

\n

Accessibility & Accommodations

\n

We’re committed to making our hiring process accessible to everyone. If you need accommodations at any stage, just reach out to us at hiring@upscaleai.com—we’re happy to help. Note: This inbox is only for accommodation requests.

","categories":{"commitment":"Reg - Full-Time","location":"India - Bangalore","team":"ASIC Engineering","allLocations":["India - Bangalore"]},"createdAt":1783616029729,"descriptionPlain":"Why join Upscale, Inc. \nUpscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.\nWe focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.\nIf you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. \n","description":"

Why join Upscale, Inc. 

\n

Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

\n

We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

\n

If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. 


\n
Role Summary:
As a Principal Engineer – Physical Design, you will be responsible for leading the implementation of complex, high-performance ASIC/SoC blocks from RTL to GDSII. You will drive design execution, define physical implementation strategies, and mentor engineers to achieve best-in-class Power, Performance, and Area (PPA) across advanced technology nodes.
\n
 
\n
Key Responsibilities:
\n\n

Required Skills & Experience:
\n\n

Preferred Skills:
\n\n

Key Traits for Success:
\n\n
 
\n
","id":"8160d67a-c69c-4326-9dff-cb16518e2f3a","lists":[],"text":"Principal Engineer – Physical Design","country":"IN","workplaceType":"onsite","opening":"

Why join Upscale, Inc. 

\n

Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

\n

We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

\n

If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. 

","openingPlain":"Why join Upscale, Inc. \nUpscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.\nWe focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.\nIf you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. \n","descriptionBody":"
\n
Role Summary:
As a Principal Engineer – Physical Design, you will be responsible for leading the implementation of complex, high-performance ASIC/SoC blocks from RTL to GDSII. You will drive design execution, define physical implementation strategies, and mentor engineers to achieve best-in-class Power, Performance, and Area (PPA) across advanced technology nodes.
\n
 
\n
Key Responsibilities:
\n\n

Required Skills & Experience:
\n\n

Preferred Skills:
\n\n

Key Traits for Success:
\n\n
 
\n
","descriptionBodyPlain":"","hostedUrl":"https://jobs.lever.co/upscale-ai/8160d67a-c69c-4326-9dff-cb16518e2f3a","applyUrl":"https://jobs.lever.co/upscale-ai/8160d67a-c69c-4326-9dff-cb16518e2f3a/apply"},{"additionalPlain":"Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.\nEqual Opportunity\nUpscale, Inc., is building a team that reflects a wide range of perspectives, backgrounds, and experiences. We’re proud to be an Equal Opportunity Employer and consider all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, disability, or veteran status.\nAccessibility & Accommodations\nWe’re committed to making our hiring process accessible to everyone. If you need accommodations at any stage, just reach out to us at hiring@upscaleai.com—we’re happy to help. Note: This inbox is only for accommodation requests.\n","additional":"

Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.

\n

Equal Opportunity

\n

Upscale, Inc., is building a team that reflects a wide range of perspectives, backgrounds, and experiences. We’re proud to be an Equal Opportunity Employer and consider all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, disability, or veteran status.

\n

Accessibility & Accommodations

\n

We’re committed to making our hiring process accessible to everyone. If you need accommodations at any stage, just reach out to us at hiring@upscaleai.com—we’re happy to help. Note: This inbox is only for accommodation requests.

","categories":{"commitment":"Reg - Full-Time","location":"India - Bangalore","team":"ASIC AI","allLocations":["India - Bangalore"]},"createdAt":1787200560115,"descriptionPlain":"Why join Upscale, Inc. \nUpscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.\nWe focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.\nIf you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. \n","description":"

Why join Upscale, Inc. 

\n

Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

\n

We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

\n

If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. 


This is a full-time, on-site Principal ASIC Designer role based in the Greater Bengaluru Area. The individual will be responsible for end-to-end ASIC design activities, including architecture exploration, micro-architecture definition, logic design and RTL development.

Qualifications:
- Solid background in Digital IC Design, including micro-architecture, RTL design, logic synthesis, timing closure, and low-power design techniques.

- Familiarity with industry-standard EDA tools (e.g., Cadence, Synopsys, Mentor) for simulation, synthesis, and static timing analysis.

- Knowledge of ASIC design flows, verification methodologies, and an ability to collaborate with physical design and validation teams.

- Bachelor’s or Master’s degree in Electrical Engineering, Electronics, or a related field (or equivalent practical experience).

- Strong problem-solving skills, attention to detail, and an ability to work collaboratively in a cross-functional, on-site team environment.

- Passionate about ASIC innovation and getting defect-free ASICs to production while meeting time-to-market challenges

- Track record of success with multiple ASIC tape-outs

- 10+ years of industry experience in ASIC design. 

- Experience with networking ASIC design is a plus.

- Experience in post-silicon ASIC bring-up is a plus.
","id":"a26a36dd-47fa-47a5-992d-fef262c93756","lists":[],"text":"Principal Engineer_RTL Design","country":"IN","workplaceType":"onsite","opening":"

Why join Upscale, Inc. 

\n

Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

\n

We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

\n

If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. 

","openingPlain":"Why join Upscale, Inc. \nUpscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.\nWe focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.\nIf you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. \n","descriptionBody":"
This is a full-time, on-site Principal ASIC Designer role based in the Greater Bengaluru Area. The individual will be responsible for end-to-end ASIC design activities, including architecture exploration, micro-architecture definition, logic design and RTL development.

Qualifications:
- Solid background in Digital IC Design, including micro-architecture, RTL design, logic synthesis, timing closure, and low-power design techniques.

- Familiarity with industry-standard EDA tools (e.g., Cadence, Synopsys, Mentor) for simulation, synthesis, and static timing analysis.

- Knowledge of ASIC design flows, verification methodologies, and an ability to collaborate with physical design and validation teams.

- Bachelor’s or Master’s degree in Electrical Engineering, Electronics, or a related field (or equivalent practical experience).

- Strong problem-solving skills, attention to detail, and an ability to work collaboratively in a cross-functional, on-site team environment.

- Passionate about ASIC innovation and getting defect-free ASICs to production while meeting time-to-market challenges

- Track record of success with multiple ASIC tape-outs

- 10+ years of industry experience in ASIC design. 

- Experience with networking ASIC design is a plus.

- Experience in post-silicon ASIC bring-up is a plus.
","descriptionBodyPlain":"","hostedUrl":"https://jobs.lever.co/upscale-ai/a26a36dd-47fa-47a5-992d-fef262c93756","applyUrl":"https://jobs.lever.co/upscale-ai/a26a36dd-47fa-47a5-992d-fef262c93756/apply"},{"additionalPlain":"Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.\nEqual Opportunity\nUpscale, Inc., is building a team that reflects a wide range of perspectives, backgrounds, and experiences. We’re proud to be an Equal Opportunity Employer and consider all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, disability, or veteran status.\nAccessibility & Accommodations\nWe’re committed to making our hiring process accessible to everyone. If you need accommodations at any stage, just reach out to us at hiring@upscaleai.com—we’re happy to help. Note: This inbox is only for accommodation requests.\n","additional":"

Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.

\n

Equal Opportunity

\n

Upscale, Inc., is building a team that reflects a wide range of perspectives, backgrounds, and experiences. We’re proud to be an Equal Opportunity Employer and consider all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, disability, or veteran status.

\n

Accessibility & Accommodations

\n

We’re committed to making our hiring process accessible to everyone. If you need accommodations at any stage, just reach out to us at hiring@upscaleai.com—we’re happy to help. Note: This inbox is only for accommodation requests.

","categories":{"commitment":"Reg - Full-Time","location":"India - Bangalore","team":"AI Network Software","allLocations":["India - Bangalore"]},"createdAt":1784698633730,"descriptionPlain":"Why join Upscale, Inc. \nUpscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.\nWe focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.\nIf you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. \n\n\nPrincipal Engineer: SDK, SAI & Platform Debugging\n \nWe are looking for a seasoned networking software professional with 12+ years of industry experience in switch software, ASIC SDKs, and network operating systems. This role is intended for an experienced engineer who can independently lead complex technical investigations, drive cross-functional problem resolution, and act as the go-to expert for SDK, SAI, and platform-related issues.\n \nThe ideal candidate should have extensive experience debugging across the entire networking software stack, including SAI, SDK, NOS, Linux kernel, platform drivers, and hardware interfaces. Beyond troubleshooting, the candidate is expected to influence architecture, guide engineering teams, engage directly with silicon vendors, and establish best practices for platform stability and supportability.\n \nWhat will you do ?\nProvide guidance on SDK-SAI integration and platform software design. Drive technical reviews and influence software design decisions to improve debuggability, reliability and maintainability of the Network Operating System (NOS).\nAnalyze SDK-SAI interactions and identify functional, performance, or scalability bottlenecks.\nServe as a lead for SDK- and SAI-related escalations across product development and customer deployments. Lead investigation and resolution of complex issues involving ASIC SDKs, SAI implementations, and switching platforms.\nOwn end-to-end root cause analysis of critical platform, feature, performance, and scale issues. Coordinate across development, QA, platform, silicon vendors, and support teams to drive issue resolution. Work closely with ASIC vendors while debugging SDK defects, feature gaps, and interoperability issues. \nAnalyze crashes, memory leaks, packet drops, forwarding inconsistencies, and hardware-software interaction issues. Debug issues spanning SDK, SAI, Platform software, Linux kernel, Hardware abstraction layers, Control and data plane components\nMentor and coach engineers on troubleshooting methodologies, debugging techniques, and networking fundamentals.\n \nWho you are?\nBachelor's or master's degree in computer science, Electronics, Telecommunications.\n12–18 years of experience in networking, software development, SDK Debugging & Troubleshooting. \nProven track record of leading complex SDK debugging and issue resolution efforts. Strong Linux system debugging and networking stack knowledge.\nStrong hands-on expertise with at least one networking switch SDKs viz. Broadcom, Marvell, Cisco Silicon One, or similar merchant silicon SDKs\nDeep understanding of SAI architecture, APIs, and SDK-SAI Interface and models.\nGood understanding of Switching ASICs, Linux Networking, Linux Networking, Packet Flow Analysis\nStrong expertise in:\nEthernet Switching\nL2/L3 Forwarding\nVLAN, STP, LACP, ACLs, QOS, ECMP, ACLs, QOS, ECMP, BGP, VXLAN/EVPN and Routing protocols\nProficiency in C/C++ and Python.\nDesirable:\nDirect engagement with silicon vendors for issue triage and feature enablement.\nExposure to hyperscale, cloud, or datacenter networking environments.\nExposure on SONiC, Platform Bring-up, NVIDIA Spectrum Series SDK Diagnostics\nAutomation & Test Frameworks\n \n","description":"

Why join Upscale, Inc. 

\n

Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

\n

We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

\n

If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. 


\n
Principal Engineer: SDK, SAI & Platform Debugging
\n
 
\n
We are looking for a seasoned networking software professional with 12+ years of industry experience in switch software, ASIC SDKs, and network operating systems. This role is intended for an experienced engineer who can independently lead complex technical investigations, drive cross-functional problem resolution, and act as the go-to expert for SDK, SAI, and platform-related issues.
\n
 
\n
The ideal candidate should have extensive experience debugging across the entire networking software stack, including SAI, SDK, NOS, Linux kernel, platform drivers, and hardware interfaces. Beyond troubleshooting, the candidate is expected to influence architecture, guide engineering teams, engage directly with silicon vendors, and establish best practices for platform stability and supportability.
\n
 
\n

What will you do ?

\n\n
 
\n

Who you are?

\n\n
Desirable:
\n\n
 
\n
","id":"b49482aa-a281-414b-bffd-19d04476017e","lists":[],"text":"Principal Engineer_SDK, SAI & Platform Debugging","country":"IN","workplaceType":"onsite","opening":"

Why join Upscale, Inc. 

\n

Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

\n

We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

\n

If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. 

","openingPlain":"Why join Upscale, Inc. \nUpscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.\nWe focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.\nIf you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. \n","descriptionBody":"
\n
Principal Engineer: SDK, SAI & Platform Debugging
\n
 
\n
We are looking for a seasoned networking software professional with 12+ years of industry experience in switch software, ASIC SDKs, and network operating systems. This role is intended for an experienced engineer who can independently lead complex technical investigations, drive cross-functional problem resolution, and act as the go-to expert for SDK, SAI, and platform-related issues.
\n
 
\n
The ideal candidate should have extensive experience debugging across the entire networking software stack, including SAI, SDK, NOS, Linux kernel, platform drivers, and hardware interfaces. Beyond troubleshooting, the candidate is expected to influence architecture, guide engineering teams, engage directly with silicon vendors, and establish best practices for platform stability and supportability.
\n
 
\n

What will you do ?

\n\n
 
\n

Who you are?

\n\n
Desirable:
\n\n
 
\n
","descriptionBodyPlain":"Principal Engineer: SDK, SAI & Platform Debugging\n \nWe are looking for a seasoned networking software professional with 12+ years of industry experience in switch software, ASIC SDKs, and network operating systems. This role is intended for an experienced engineer who can independently lead complex technical investigations, drive cross-functional problem resolution, and act as the go-to expert for SDK, SAI, and platform-related issues.\n \nThe ideal candidate should have extensive experience debugging across the entire networking software stack, including SAI, SDK, NOS, Linux kernel, platform drivers, and hardware interfaces. Beyond troubleshooting, the candidate is expected to influence architecture, guide engineering teams, engage directly with silicon vendors, and establish best practices for platform stability and supportability.\n \nWhat will you do ?\nProvide guidance on SDK-SAI integration and platform software design. Drive technical reviews and influence software design decisions to improve debuggability, reliability and maintainability of the Network Operating System (NOS).\nAnalyze SDK-SAI interactions and identify functional, performance, or scalability bottlenecks.\nServe as a lead for SDK- and SAI-related escalations across product development and customer deployments. Lead investigation and resolution of complex issues involving ASIC SDKs, SAI implementations, and switching platforms.\nOwn end-to-end root cause analysis of critical platform, feature, performance, and scale issues. Coordinate across development, QA, platform, silicon vendors, and support teams to drive issue resolution. Work closely with ASIC vendors while debugging SDK defects, feature gaps, and interoperability issues. \nAnalyze crashes, memory leaks, packet drops, forwarding inconsistencies, and hardware-software interaction issues. Debug issues spanning SDK, SAI, Platform software, Linux kernel, Hardware abstraction layers, Control and data plane components\nMentor and coach engineers on troubleshooting methodologies, debugging techniques, and networking fundamentals.\n \nWho you are?\nBachelor's or master's degree in computer science, Electronics, Telecommunications.\n12–18 years of experience in networking, software development, SDK Debugging & Troubleshooting. \nProven track record of leading complex SDK debugging and issue resolution efforts. Strong Linux system debugging and networking stack knowledge.\nStrong hands-on expertise with at least one networking switch SDKs viz. Broadcom, Marvell, Cisco Silicon One, or similar merchant silicon SDKs\nDeep understanding of SAI architecture, APIs, and SDK-SAI Interface and models.\nGood understanding of Switching ASICs, Linux Networking, Linux Networking, Packet Flow Analysis\nStrong expertise in:\nEthernet Switching\nL2/L3 Forwarding\nVLAN, STP, LACP, ACLs, QOS, ECMP, ACLs, QOS, ECMP, BGP, VXLAN/EVPN and Routing protocols\nProficiency in C/C++ and Python.\nDesirable:\nDirect engagement with silicon vendors for issue triage and feature enablement.\nExposure to hyperscale, cloud, or datacenter networking environments.\nExposure on SONiC, Platform Bring-up, NVIDIA Spectrum Series SDK Diagnostics\nAutomation & Test Frameworks\n \n","hostedUrl":"https://jobs.lever.co/upscale-ai/b49482aa-a281-414b-bffd-19d04476017e","applyUrl":"https://jobs.lever.co/upscale-ai/b49482aa-a281-414b-bffd-19d04476017e/apply"},{"additionalPlain":"Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.\nEqual Opportunity\nUpscale, Inc., is building a team that reflects a wide range of perspectives, backgrounds, and experiences. We’re proud to be an Equal Opportunity Employer and consider all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, disability, or veteran status.\nAccessibility & Accommodations\nWe’re committed to making our hiring process accessible to everyone. If you need accommodations at any stage, just reach out to us at hiring@upscaleai.com—we’re happy to help. Note: This inbox is only for accommodation requests.\n","additional":"

Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.

\n

Equal Opportunity

\n

Upscale, Inc., is building a team that reflects a wide range of perspectives, backgrounds, and experiences. We’re proud to be an Equal Opportunity Employer and consider all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, disability, or veteran status.

\n

Accessibility & Accommodations

\n

We’re committed to making our hiring process accessible to everyone. If you need accommodations at any stage, just reach out to us at hiring@upscaleai.com—we’re happy to help. Note: This inbox is only for accommodation requests.

","categories":{"commitment":"Reg - Full-Time","location":"US - Headquarters","team":"Direct Sales","allLocations":["US - Headquarters"]},"createdAt":1790112511769,"descriptionPlain":"Why join Upscale, Inc. \nUpscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.\nWe focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.\nIf you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. \n","description":"

Why join Upscale, Inc. 

\n

Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

\n

We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

\n

If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. 


\n

Position Overview

\n

We are seeking a highly motivated and technically proficient Sales Engineer to drive complex solution sales across cutting-edge AI infrastructure markets. In this role, you will serve as the technical lead throughout the sales process, partnering with Account Managers, Product, and Engineering teams to understand customer requirements, design innovative solutions, and deliver compelling technical presentations and demonstrations.

\n

The ideal candidate has a strong grasp of ASIC/semiconductor-level design and tradeoffs and deep, hands-on expertise in scale-up networking and interconnect technologies alongside a solid understanding of traditional scale-out networking and modern network operating systems (e.g., SONiC, EOS, Junos). You should be fluent in the xPU/NIC ecosystem and competitive offerings, and conversant in emerging scale-up/interconnect standards such as ESUN, UALink (UAL), and SUE.

\n

You will work closely with customers to architect solutions that align with their business and technical goals, while representing their feedback internally to shape our product roadmap.

\n

This is an opportunity to make a significant impact in a fast-paced, high-growth environment, with exposure to strategic customers, emerging technologies, and industry-shaping innovations.

\n
","id":"42ebf188-a46c-466e-82f1-f486760cdbd9","lists":[{"text":"Responsibilities ","content":"
\n

·       Manage high-value global customer accounts in partnership with the Account Manager.

\n

·       Drive complex, full-cycle solution sales from ASIC-level to system-level and rack-scale deployments.

\n

·       Serve as a trusted technical advisor to customers, drawing on chip, board, and system-level expertise to guide them through solution design, evaluation, and adoption.

\n

·       Design and propose solutions leveraging Upscale’s product portfolio.

\n

·       Lead technical discovery, gather customer requirements, and develop proof-of-concept validation and demos to demonstrate product and solution capabilities across AI clusters - GPU, NIC, xPU, and switch tray platforms.

\n

·  Deliver compelling technical presentations, product demonstrations, and feature deep-dives to customer stakeholders.

\n

·       Identify and develop new business opportunities within both existing and prospective accounts.

\n

·       Collaborate with Sales and Product teams to respond to RFPs, RFIs, RFQs, and other sales proposals with tailored technical input on ASIC, scale-up interconnect, and networking architecture.

\n

·       Partner cross-functionally with engineering, product management, and operations teams to deliver on customer requirements and align product roadmaps with market needs, including emerging standards such as ESUN, SUE, ETH, IP and UALink.

\n

·    Represent Upscale at industry events, conferences, and technical forums; contribute thought leadership through white papers and technical publications on AI scale-up networking and semiconductor architecture.

\n

·       Continuously invest in professional development by pursuing technical training and staying informed about industry trends, technologies, and competitive offerings.

\n
"},{"text":"Requirements ","content":"
\n

·    Minimum of 10 years of pre-sales experience as a Sales Engineer, Solutions Engineer, or Solutions Architect in the AI infrastructure, semiconductor, or networking sector. Candidates coming from a Field Application Engineering (FAE) background with strong customer-facing experience are strongly encouraged to apply.

\n

·       Proven track record in selling or supporting complex network infrastructure and semiconductor/ASIC solutions to hyperscalers, enterprise customers, and cloud providers.

\n

·    Bachelor's, Master's, or Ph.D. in Computer Science, Electrical Engineering, or a related engineering discipline, or equivalent industry experience.

\n

·       Strong foundation in ASIC/semiconductor architecture, with the ability to speak fluently to chip-level tradeoffs (power, thermals, SerDes, packaging) as they relate to system design.

\n

·      Hands-on experience with scale-up networking and interconnect technologies as well as scale-out data center and WAN networking.

\n

·      Working knowledge of major network operating systems such as SONiC, Arista EOS, Juniper Junos, Cisco IOS, etc.

\n

·       Fluency with the GPU/NIC ecosystem and familiarity with competitive xPU offerings and vendors.

\n

·       Familiarity with emerging scale-up and interconnect standards, including ESUN, UALink (UAL), and SUE.

\n

·   Clear understanding of AI-driven workloads and associated data center and network architecture requirements, including frontend and backend AI network design.

\n

·     Excellent communication, presentation, and interpersonal skills, with the ability to effectively engage with technical and executive stakeholders.

\n

·       Demonstrated ability to collaborate across cross-functional teams in sales, product, and engineering.

\n

·       Willingness and ability to travel up to 25%, including international travel.

\n
"}],"salaryRange":{"min":239000,"max":266000,"currency":"USD","interval":"per-year-salary"},"text":"Principal Sales Engineer","country":"US","workplaceType":"onsite","opening":"

Why join Upscale, Inc. 

\n

Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

\n

We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

\n

If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. 

","openingPlain":"Why join Upscale, Inc. \nUpscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.\nWe focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.\nIf you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. \n","descriptionBody":"
\n

Position Overview

\n

We are seeking a highly motivated and technically proficient Sales Engineer to drive complex solution sales across cutting-edge AI infrastructure markets. In this role, you will serve as the technical lead throughout the sales process, partnering with Account Managers, Product, and Engineering teams to understand customer requirements, design innovative solutions, and deliver compelling technical presentations and demonstrations.

\n

The ideal candidate has a strong grasp of ASIC/semiconductor-level design and tradeoffs and deep, hands-on expertise in scale-up networking and interconnect technologies alongside a solid understanding of traditional scale-out networking and modern network operating systems (e.g., SONiC, EOS, Junos). You should be fluent in the xPU/NIC ecosystem and competitive offerings, and conversant in emerging scale-up/interconnect standards such as ESUN, UALink (UAL), and SUE.

\n

You will work closely with customers to architect solutions that align with their business and technical goals, while representing their feedback internally to shape our product roadmap.

\n

This is an opportunity to make a significant impact in a fast-paced, high-growth environment, with exposure to strategic customers, emerging technologies, and industry-shaping innovations.

\n
","descriptionBodyPlain":"","hostedUrl":"https://jobs.lever.co/upscale-ai/42ebf188-a46c-466e-82f1-f486760cdbd9","applyUrl":"https://jobs.lever.co/upscale-ai/42ebf188-a46c-466e-82f1-f486760cdbd9/apply"},{"additionalPlain":"Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.\nEqual Opportunity\nUpscale, Inc., is building a team that reflects a wide range of perspectives, backgrounds, and experiences. We’re proud to be an Equal Opportunity Employer and consider all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, disability, or veteran status.\nAccessibility & Accommodations\nWe’re committed to making our hiring process accessible to everyone. If you need accommodations at any stage, just reach out to us at hiring@upscaleai.com—we’re happy to help. Note: This inbox is only for accommodation requests.\n","additional":"

Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.

\n

Equal Opportunity

\n

Upscale, Inc., is building a team that reflects a wide range of perspectives, backgrounds, and experiences. We’re proud to be an Equal Opportunity Employer and consider all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, disability, or veteran status.

\n

Accessibility & Accommodations

\n

We’re committed to making our hiring process accessible to everyone. If you need accommodations at any stage, just reach out to us at hiring@upscaleai.com—we’re happy to help. Note: This inbox is only for accommodation requests.

","categories":{"commitment":"Reg - Full-Time","location":"US - Headquarters","team":"ASIC Architecture","allLocations":["US - Headquarters"]},"createdAt":1781637117940,"descriptionPlain":"Why join Upscale, Inc. \nUpscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.\nWe focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.\nIf you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. \n\n\nPosition Overview\n\n\nAbout the Role: We're building the simulation platform for UpscaleAI's next-generation AI networking ASICs. The platform is a functionally accurate software model of our ASIC architecture, enabling software development, verification, and customer validation before silicon is available. You'll be responsible for developing, testing and maintaining the platform across multiple ASIC generations, ensuring it accurately represents hardware behavior and scales to support our customers' demanding AI infrastructure workloads. \n\n\nWhat You'll Work On: \n\nASIC Architectural Model: Our current-generation ASIC simulator\nNext-gen ASIC models: Future silicon with enhanced AI networking features\nMulti-chip simulation: Modeling systems with multiple interconnected ASICs\nPerformance optimization: Making large-scale simulations practical\n \n\n","description":"

Why join Upscale, Inc. 

\n

Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

\n

We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

\n

If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. 


\n

Position Overview

\n



About the Role:
We're building the simulation platform for UpscaleAI's next-generation AI networking ASICs. The platform is a functionally accurate software model of our ASIC architecture, enabling software development, verification, and customer validation before silicon is available. You'll be responsible for developing, testing and maintaining the platform across multiple ASIC generations, ensuring it accurately represents hardware behavior and scales to support our customers' demanding AI infrastructure workloads. 

\n


What You'll Work On: 

\n\n

 

\n
","id":"4efcf740-79ac-45be-a587-4898b28302ec","lists":[{"text":"Key Responsibilities ","content":"
\n
"}],"salaryRange":{"min":159000,"max":178000,"currency":"USD","interval":"per-year-salary"},"text":"Senior ASIC Modeling Software Engineer","country":"US","workplaceType":"onsite","opening":"

Why join Upscale, Inc. 

\n

Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

\n

We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

\n

If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. 

","openingPlain":"Why join Upscale, Inc. \nUpscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.\nWe focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.\nIf you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. \n","descriptionBody":"
\n

Position Overview

\n



About the Role:
We're building the simulation platform for UpscaleAI's next-generation AI networking ASICs. The platform is a functionally accurate software model of our ASIC architecture, enabling software development, verification, and customer validation before silicon is available. You'll be responsible for developing, testing and maintaining the platform across multiple ASIC generations, ensuring it accurately represents hardware behavior and scales to support our customers' demanding AI infrastructure workloads. 

\n


What You'll Work On: 

\n\n

 

\n
","descriptionBodyPlain":"Position Overview\n\n\nAbout the Role: We're building the simulation platform for UpscaleAI's next-generation AI networking ASICs. The platform is a functionally accurate software model of our ASIC architecture, enabling software development, verification, and customer validation before silicon is available. You'll be responsible for developing, testing and maintaining the platform across multiple ASIC generations, ensuring it accurately represents hardware behavior and scales to support our customers' demanding AI infrastructure workloads. \n\n\nWhat You'll Work On: \n\nASIC Architectural Model: Our current-generation ASIC simulator\nNext-gen ASIC models: Future silicon with enhanced AI networking features\nMulti-chip simulation: Modeling systems with multiple interconnected ASICs\nPerformance optimization: Making large-scale simulations practical\n \n\n","hostedUrl":"https://jobs.lever.co/upscale-ai/4efcf740-79ac-45be-a587-4898b28302ec","applyUrl":"https://jobs.lever.co/upscale-ai/4efcf740-79ac-45be-a587-4898b28302ec/apply"},{"additionalPlain":"Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.\nEqual Opportunity\nUpscale, Inc., is building a team that reflects a wide range of perspectives, backgrounds, and experiences. We’re proud to be an Equal Opportunity Employer and consider all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, disability, or veteran status.\nAccessibility & Accommodations\nWe’re committed to making our hiring process accessible to everyone. If you need accommodations at any stage, just reach out to us at hiring@upscaleai.com—we’re happy to help. Note: This inbox is only for accommodation requests.\n","additional":"

Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.

\n

Equal Opportunity

\n

Upscale, Inc., is building a team that reflects a wide range of perspectives, backgrounds, and experiences. We’re proud to be an Equal Opportunity Employer and consider all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, disability, or veteran status.

\n

Accessibility & Accommodations

\n

We’re committed to making our hiring process accessible to everyone. If you need accommodations at any stage, just reach out to us at hiring@upscaleai.com—we’re happy to help. Note: This inbox is only for accommodation requests.

","categories":{"commitment":"Reg - Full-Time","location":"India - Bangalore","team":"ASIC Engineering","allLocations":["India - Bangalore"]},"createdAt":1783616132290,"descriptionPlain":"Why join Upscale, Inc. \nUpscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.\nWe focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.\nIf you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. \n\n\nRole Summary:As a Senior Back End Manager – Physical Design, you will be responsible for leading high-performance ASIC/SoC physical implementation teams delivering complex designs from RTL to GDSII. You will drive execution strategy, build scalable methodologies, manage technical execution across multiple blocks/subsystems, and ensure successful design convergence across advanced technology nodes.\nThe role requires a strong technical leader with hands-on expertise in physical design, proven ability to manage engineering teams, and experience delivering large-scale silicon programs with aggressive Power, Performance, Area, and Schedule targets.\nKey Responsibilities:\nLead and manage a team of Physical Design engineers responsible for implementation and signoff of complex ASIC/SoC designs.\nOwn overall back-end execution strategy including floorplanning, placement, CTS, routing, timing closure, physical verification, and tape-out readiness.\nDrive project planning, resource allocation, execution tracking, risk identification, and mitigation across multiple design milestones.\nProvide technical leadership for architecture decisions including hierarchy definition, partitioning strategy, clock architecture, power planning, and implementation methodology.\nCollaborate closely with Architecture, RTL, DFT, STA, CAD, Packaging, Foundry, and Program Management teams to achieve successful silicon delivery.\nDrive convergence across PPA, timing, power, IR/EM, signal integrity, DRC/LVS, reliability, and manufacturability requirements.\nEstablish robust execution methodologies, quality checks, automation flows, and best practices across the Back End organization.\nReview design quality at key milestones and ensure strong execution discipline through structured reviews and predictable delivery.\nLead debug and resolution of complex design challenges across timing, congestion, power, physical verification, and ECO implementation.\nPartner with CAD and EDA vendors to improve flows, evaluate new technologies, and enhance design productivity.\nMentor engineers, technical leads, and future leaders while building a culture of ownership, innovation, accountability, and engineering excellence.\nRequired Skills & Experience:\n15–20 years of experience in ASIC/SoC Physical Design with strong experience managing large Back End implementation teams.\nProven track record of delivering complex SoC designs successfully through tape-out on advanced technology nodes.\nDeep expertise in physical implementation flows including floorplan, power planning, placement, CTS, routing, ECO, and signoff closure.\nStrong experience with Cadence Innovus based implementation flows.\nExpert-level understanding of STA (PrimeTime), IR/EM analysis (Voltus/RedHawk), physical verification (Calibre/ICV), and extraction methodologies.\nHands-on experience with advanced process nodes (5 nm / 3 nm / N3E/N3P) and foundry signoff requirements.\nStrong understanding of hierarchical design methodologies, multi-voltage designs, UPF, clock distribution strategies, and MCMM closure.\nExperience defining metrics, dashboards, quality checks, and execution processes for predictable project delivery.\nStrong scripting and automation mindset using Tcl, Perl, Python, or equivalent languages.\nExcellent leadership, communication, decision-making, and cross-functional collaboration skills.\nPreferred Skills:\nExperience leading full-chip implementation and large subsystem ownership.\nExposure to AI/HPC/networking class SoCs with aggressive performance and power requirements.\nExperience building teams, defining organizational processes, and scaling execution methodologies.\nKnowledge of ML-driven EDA optimization and next-generation design methodologies is a plus.\nMaster’s Degree in Electrical Engineering / Electronics / VLSI Engineering preferred.\nKey Traits for Success:\nStrong technical depth combined with execution leadership.\nOwnership mindset with the ability to drive complex programs to closure.\nAbility to identify risks early and create structured recovery plans.\nPassion for building high-performing teams and mentoring engineers.\nData-driven decision making with focus on quality, predictability, and continuous improvement.\nAbility to balance innovation, schedule pressure, and silicon delivery excellence.\n","description":"

Why join Upscale, Inc. 

\n

Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

\n

We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

\n

If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. 


\n

Role Summary:
As a Senior Back End Manager – Physical Design, you will be responsible for leading high-performance ASIC/SoC physical implementation teams delivering complex designs from RTL to GDSII. You will drive execution strategy, build scalable methodologies, manage technical execution across multiple blocks/subsystems, and ensure successful design convergence across advanced technology nodes.

\n

The role requires a strong technical leader with hands-on expertise in physical design, proven ability to manage engineering teams, and experience delivering large-scale silicon programs with aggressive Power, Performance, Area, and Schedule targets.

\n

Key Responsibilities:

\n

Lead and manage a team of Physical Design engineers responsible for implementation and signoff of complex ASIC/SoC designs.

\n

Own overall back-end execution strategy including floorplanning, placement, CTS, routing, timing closure, physical verification, and tape-out readiness.

\n

Drive project planning, resource allocation, execution tracking, risk identification, and mitigation across multiple design milestones.

\n

Provide technical leadership for architecture decisions including hierarchy definition, partitioning strategy, clock architecture, power planning, and implementation methodology.

\n

Collaborate closely with Architecture, RTL, DFT, STA, CAD, Packaging, Foundry, and Program Management teams to achieve successful silicon delivery.

\n

Drive convergence across PPA, timing, power, IR/EM, signal integrity, DRC/LVS, reliability, and manufacturability requirements.

\n

Establish robust execution methodologies, quality checks, automation flows, and best practices across the Back End organization.

\n

Review design quality at key milestones and ensure strong execution discipline through structured reviews and predictable delivery.

\n

Lead debug and resolution of complex design challenges across timing, congestion, power, physical verification, and ECO implementation.

\n

Partner with CAD and EDA vendors to improve flows, evaluate new technologies, and enhance design productivity.

\n

Mentor engineers, technical leads, and future leaders while building a culture of ownership, innovation, accountability, and engineering excellence.

\n

Required Skills & Experience:

\n

15–20 years of experience in ASIC/SoC Physical Design with strong experience managing large Back End implementation teams.

\n

Proven track record of delivering complex SoC designs successfully through tape-out on advanced technology nodes.

\n

Deep expertise in physical implementation flows including floorplan, power planning, placement, CTS, routing, ECO, and signoff closure.

\n

Strong experience with Cadence Innovus based implementation flows.

\n

Expert-level understanding of STA (PrimeTime), IR/EM analysis (Voltus/RedHawk), physical verification (Calibre/ICV), and extraction methodologies.

\n

Hands-on experience with advanced process nodes (5 nm / 3 nm / N3E/N3P) and foundry signoff requirements.

\n

Strong understanding of hierarchical design methodologies, multi-voltage designs, UPF, clock distribution strategies, and MCMM closure.

\n

Experience defining metrics, dashboards, quality checks, and execution processes for predictable project delivery.

\n

Strong scripting and automation mindset using Tcl, Perl, Python, or equivalent languages.

\n

Excellent leadership, communication, decision-making, and cross-functional collaboration skills.

\n

Preferred Skills:

\n

Experience leading full-chip implementation and large subsystem ownership.

\n

Exposure to AI/HPC/networking class SoCs with aggressive performance and power requirements.

\n

Experience building teams, defining organizational processes, and scaling execution methodologies.

\n

Knowledge of ML-driven EDA optimization and next-generation design methodologies is a plus.

\n

Master’s Degree in Electrical Engineering / Electronics / VLSI Engineering preferred.

\n

Key Traits for Success:

\n

Strong technical depth combined with execution leadership.

\n

Ownership mindset with the ability to drive complex programs to closure.

\n

Ability to identify risks early and create structured recovery plans.

\n

Passion for building high-performing teams and mentoring engineers.

\n

Data-driven decision making with focus on quality, predictability, and continuous improvement.

\n

Ability to balance innovation, schedule pressure, and silicon delivery excellence.

\n
","id":"d3366d3e-11e3-4c1a-b615-580d4a9b336b","lists":[],"text":"Senior Manager – Physical Design","country":"IN","workplaceType":"onsite","opening":"

Why join Upscale, Inc. 

\n

Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

\n

We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

\n

If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. 

","openingPlain":"Why join Upscale, Inc. \nUpscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.\nWe focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.\nIf you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. \n","descriptionBody":"
\n

Role Summary:
As a Senior Back End Manager – Physical Design, you will be responsible for leading high-performance ASIC/SoC physical implementation teams delivering complex designs from RTL to GDSII. You will drive execution strategy, build scalable methodologies, manage technical execution across multiple blocks/subsystems, and ensure successful design convergence across advanced technology nodes.

\n

The role requires a strong technical leader with hands-on expertise in physical design, proven ability to manage engineering teams, and experience delivering large-scale silicon programs with aggressive Power, Performance, Area, and Schedule targets.

\n

Key Responsibilities:

\n

Lead and manage a team of Physical Design engineers responsible for implementation and signoff of complex ASIC/SoC designs.

\n

Own overall back-end execution strategy including floorplanning, placement, CTS, routing, timing closure, physical verification, and tape-out readiness.

\n

Drive project planning, resource allocation, execution tracking, risk identification, and mitigation across multiple design milestones.

\n

Provide technical leadership for architecture decisions including hierarchy definition, partitioning strategy, clock architecture, power planning, and implementation methodology.

\n

Collaborate closely with Architecture, RTL, DFT, STA, CAD, Packaging, Foundry, and Program Management teams to achieve successful silicon delivery.

\n

Drive convergence across PPA, timing, power, IR/EM, signal integrity, DRC/LVS, reliability, and manufacturability requirements.

\n

Establish robust execution methodologies, quality checks, automation flows, and best practices across the Back End organization.

\n

Review design quality at key milestones and ensure strong execution discipline through structured reviews and predictable delivery.

\n

Lead debug and resolution of complex design challenges across timing, congestion, power, physical verification, and ECO implementation.

\n

Partner with CAD and EDA vendors to improve flows, evaluate new technologies, and enhance design productivity.

\n

Mentor engineers, technical leads, and future leaders while building a culture of ownership, innovation, accountability, and engineering excellence.

\n

Required Skills & Experience:

\n

15–20 years of experience in ASIC/SoC Physical Design with strong experience managing large Back End implementation teams.

\n

Proven track record of delivering complex SoC designs successfully through tape-out on advanced technology nodes.

\n

Deep expertise in physical implementation flows including floorplan, power planning, placement, CTS, routing, ECO, and signoff closure.

\n

Strong experience with Cadence Innovus based implementation flows.

\n

Expert-level understanding of STA (PrimeTime), IR/EM analysis (Voltus/RedHawk), physical verification (Calibre/ICV), and extraction methodologies.

\n

Hands-on experience with advanced process nodes (5 nm / 3 nm / N3E/N3P) and foundry signoff requirements.

\n

Strong understanding of hierarchical design methodologies, multi-voltage designs, UPF, clock distribution strategies, and MCMM closure.

\n

Experience defining metrics, dashboards, quality checks, and execution processes for predictable project delivery.

\n

Strong scripting and automation mindset using Tcl, Perl, Python, or equivalent languages.

\n

Excellent leadership, communication, decision-making, and cross-functional collaboration skills.

\n

Preferred Skills:

\n

Experience leading full-chip implementation and large subsystem ownership.

\n

Exposure to AI/HPC/networking class SoCs with aggressive performance and power requirements.

\n

Experience building teams, defining organizational processes, and scaling execution methodologies.

\n

Knowledge of ML-driven EDA optimization and next-generation design methodologies is a plus.

\n

Master’s Degree in Electrical Engineering / Electronics / VLSI Engineering preferred.

\n

Key Traits for Success:

\n

Strong technical depth combined with execution leadership.

\n

Ownership mindset with the ability to drive complex programs to closure.

\n

Ability to identify risks early and create structured recovery plans.

\n

Passion for building high-performing teams and mentoring engineers.

\n

Data-driven decision making with focus on quality, predictability, and continuous improvement.

\n

Ability to balance innovation, schedule pressure, and silicon delivery excellence.

\n
","descriptionBodyPlain":"Role Summary:As a Senior Back End Manager – Physical Design, you will be responsible for leading high-performance ASIC/SoC physical implementation teams delivering complex designs from RTL to GDSII. You will drive execution strategy, build scalable methodologies, manage technical execution across multiple blocks/subsystems, and ensure successful design convergence across advanced technology nodes.\nThe role requires a strong technical leader with hands-on expertise in physical design, proven ability to manage engineering teams, and experience delivering large-scale silicon programs with aggressive Power, Performance, Area, and Schedule targets.\nKey Responsibilities:\nLead and manage a team of Physical Design engineers responsible for implementation and signoff of complex ASIC/SoC designs.\nOwn overall back-end execution strategy including floorplanning, placement, CTS, routing, timing closure, physical verification, and tape-out readiness.\nDrive project planning, resource allocation, execution tracking, risk identification, and mitigation across multiple design milestones.\nProvide technical leadership for architecture decisions including hierarchy definition, partitioning strategy, clock architecture, power planning, and implementation methodology.\nCollaborate closely with Architecture, RTL, DFT, STA, CAD, Packaging, Foundry, and Program Management teams to achieve successful silicon delivery.\nDrive convergence across PPA, timing, power, IR/EM, signal integrity, DRC/LVS, reliability, and manufacturability requirements.\nEstablish robust execution methodologies, quality checks, automation flows, and best practices across the Back End organization.\nReview design quality at key milestones and ensure strong execution discipline through structured reviews and predictable delivery.\nLead debug and resolution of complex design challenges across timing, congestion, power, physical verification, and ECO implementation.\nPartner with CAD and EDA vendors to improve flows, evaluate new technologies, and enhance design productivity.\nMentor engineers, technical leads, and future leaders while building a culture of ownership, innovation, accountability, and engineering excellence.\nRequired Skills & Experience:\n15–20 years of experience in ASIC/SoC Physical Design with strong experience managing large Back End implementation teams.\nProven track record of delivering complex SoC designs successfully through tape-out on advanced technology nodes.\nDeep expertise in physical implementation flows including floorplan, power planning, placement, CTS, routing, ECO, and signoff closure.\nStrong experience with Cadence Innovus based implementation flows.\nExpert-level understanding of STA (PrimeTime), IR/EM analysis (Voltus/RedHawk), physical verification (Calibre/ICV), and extraction methodologies.\nHands-on experience with advanced process nodes (5 nm / 3 nm / N3E/N3P) and foundry signoff requirements.\nStrong understanding of hierarchical design methodologies, multi-voltage designs, UPF, clock distribution strategies, and MCMM closure.\nExperience defining metrics, dashboards, quality checks, and execution processes for predictable project delivery.\nStrong scripting and automation mindset using Tcl, Perl, Python, or equivalent languages.\nExcellent leadership, communication, decision-making, and cross-functional collaboration skills.\nPreferred Skills:\nExperience leading full-chip implementation and large subsystem ownership.\nExposure to AI/HPC/networking class SoCs with aggressive performance and power requirements.\nExperience building teams, defining organizational processes, and scaling execution methodologies.\nKnowledge of ML-driven EDA optimization and next-generation design methodologies is a plus.\nMaster’s Degree in Electrical Engineering / Electronics / VLSI Engineering preferred.\nKey Traits for Success:\nStrong technical depth combined with execution leadership.\nOwnership mindset with the ability to drive complex programs to closure.\nAbility to identify risks early and create structured recovery plans.\nPassion for building high-performing teams and mentoring engineers.\nData-driven decision making with focus on quality, predictability, and continuous improvement.\nAbility to balance innovation, schedule pressure, and silicon delivery excellence.\n","hostedUrl":"https://jobs.lever.co/upscale-ai/d3366d3e-11e3-4c1a-b615-580d4a9b336b","applyUrl":"https://jobs.lever.co/upscale-ai/d3366d3e-11e3-4c1a-b615-580d4a9b336b/apply"},{"additionalPlain":"Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.\nEqual Opportunity\nUpscale, Inc., is building a team that reflects a wide range of perspectives, backgrounds, and experiences. We’re proud to be an Equal Opportunity Employer and consider all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, disability, or veteran status.\nAccessibility & Accommodations\nWe’re committed to making our hiring process accessible to everyone. If you need accommodations at any stage, just reach out to us at hiring@upscaleai.com—we’re happy to help. Note: This inbox is only for accommodation requests.\n","additional":"

Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.

\n

Equal Opportunity

\n

Upscale, Inc., is building a team that reflects a wide range of perspectives, backgrounds, and experiences. We’re proud to be an Equal Opportunity Employer and consider all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, disability, or veteran status.

\n

Accessibility & Accommodations

\n

We’re committed to making our hiring process accessible to everyone. If you need accommodations at any stage, just reach out to us at hiring@upscaleai.com—we’re happy to help. Note: This inbox is only for accommodation requests.

","categories":{"commitment":"Reg - Full-Time","location":"India - Bangalore","team":"ASIC AI","allLocations":["India - Bangalore"]},"createdAt":1784014406752,"descriptionPlain":"Why join Upscale, Inc. \nUpscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.\nWe focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.\nIf you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. \n\n\nExperience Level: 17+ Years (or 15+ with exceptional strategic track record)\nLocation: Bangalore, India (On-Site)\nPosition Type: Full-Time\nAbout the Role\nWe are seeking a visionary Senior Principal DV Engineer to define the global verification strategy for our massive-scale networking SoCs. This is a high-impact, elite technical leadership role. You will be responsible for defining the overarching SoC verification methodology, driving cross-functional alignment from architecture to post-silicon, and pioneering next-generation verification technologies (such as Formal and Emulation). You will influence design architectures for verifiability and serve as a strategic technical advisor to executive leadership while steering the broader engineering organization.\nKey Responsibilities\nSoC Verification Strategy: Define, architect, and govern the overarching verification roadmap and methodology for full-scale, multi-million gate networking SoCs.\nMethodology Innovation: Drive the adoption of advanced methodologies. Seamlessly integrate Formal Property Verification (FPV), hardware emulation, and advanced shift-left strategies into the standard SoC timeline.\nHigh-Level Governance: Establish, track, and enforce rigorous quality metrics and sign-off criteria across the entire project lifecycle, ensuring zero-defect silicon.\nArchitectural Influence: Work directly with Silicon Architects and Design Directors to review specs, optimize micro-architecture for testability/verifiability (DFV), and mitigate risk early.\nOrganizational Mentorship: Mentor Principal engineers and technical leads across the site. Champion best practices, drive technical brainstorming, and cultivate a culture of engineering excellence.\nCrisis Debugging & Escalation: Act as the ultimate technical authority for critical, complex issues that block project milestones or require deep cross-functional triage.\nRequired Qualifications & Skills\nExperience: 15+ to 17+ years of distinguished experience in ASIC/SoC Verification, having successfully guided multiple complex, large-scale tape-outs from concept to production.\nDomain Leadership: Deep, comprehensive knowledge of the networking domain, with an understanding of how system-level traffic flow impacts full-chip verification constraints.\nFull-Scale SoC Scope: Proven experience leading full SoC-level verification environments, managing top-level testbenches, and coordinating multi-subsystem integration.\nExpertise: Authoritative knowledge of System Verilog, UVM, and structural verification planning.\nInfluence & Communication: Outstanding executive communication skills. Ability to articulate complex technical risks and trade-offs clearly to both engineering teams and executive management.\nEducation: B Tech/M Tech in Electronics/Electrical Engineering, Computer Engineering, or a related field.\nPreferred / Added Advantages\nStrong, proven track record of deploying Formal Verification (FPV) at scale to displace traditional simulation.\nExperience integrating hardware emulation (e.g., Palladium, Zebu) into a unified simulation workflow.\n \n","description":"

Why join Upscale, Inc. 

\n

Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

\n

We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

\n

If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. 


\n
Experience Level: 17+ Years (or 15+ with exceptional strategic track record)
\n
Location: Bangalore, India (On-Site)
\n
Position Type: Full-Time
\n
About the Role
\n
We are seeking a visionary Senior Principal DV Engineer to define the global verification strategy for our massive-scale networking SoCs. This is a high-impact, elite technical leadership role. You will be responsible for defining the overarching SoC verification methodology, driving cross-functional alignment from architecture to post-silicon, and pioneering next-generation verification technologies (such as Formal and Emulation). You will influence design architectures for verifiability and serve as a strategic technical advisor to executive leadership while steering the broader engineering organization.
\n
Key Responsibilities
\n\n
Required Qualifications & Skills
\n\n
Preferred / Added Advantages
\n\n
 
\n
","id":"9149e72d-ee97-498a-a587-3546d293afb2","lists":[],"text":"Senior Principal Engineer - Design Verification","country":"IN","workplaceType":"onsite","opening":"

Why join Upscale, Inc. 

\n

Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

\n

We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

\n

If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. 

","openingPlain":"Why join Upscale, Inc. \nUpscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.\nWe focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.\nIf you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. \n","descriptionBody":"
\n
Experience Level: 17+ Years (or 15+ with exceptional strategic track record)
\n
Location: Bangalore, India (On-Site)
\n
Position Type: Full-Time
\n
About the Role
\n
We are seeking a visionary Senior Principal DV Engineer to define the global verification strategy for our massive-scale networking SoCs. This is a high-impact, elite technical leadership role. You will be responsible for defining the overarching SoC verification methodology, driving cross-functional alignment from architecture to post-silicon, and pioneering next-generation verification technologies (such as Formal and Emulation). You will influence design architectures for verifiability and serve as a strategic technical advisor to executive leadership while steering the broader engineering organization.
\n
Key Responsibilities
\n\n
Required Qualifications & Skills
\n\n
Preferred / Added Advantages
\n\n
 
\n
","descriptionBodyPlain":"Experience Level: 17+ Years (or 15+ with exceptional strategic track record)\nLocation: Bangalore, India (On-Site)\nPosition Type: Full-Time\nAbout the Role\nWe are seeking a visionary Senior Principal DV Engineer to define the global verification strategy for our massive-scale networking SoCs. This is a high-impact, elite technical leadership role. You will be responsible for defining the overarching SoC verification methodology, driving cross-functional alignment from architecture to post-silicon, and pioneering next-generation verification technologies (such as Formal and Emulation). You will influence design architectures for verifiability and serve as a strategic technical advisor to executive leadership while steering the broader engineering organization.\nKey Responsibilities\nSoC Verification Strategy: Define, architect, and govern the overarching verification roadmap and methodology for full-scale, multi-million gate networking SoCs.\nMethodology Innovation: Drive the adoption of advanced methodologies. Seamlessly integrate Formal Property Verification (FPV), hardware emulation, and advanced shift-left strategies into the standard SoC timeline.\nHigh-Level Governance: Establish, track, and enforce rigorous quality metrics and sign-off criteria across the entire project lifecycle, ensuring zero-defect silicon.\nArchitectural Influence: Work directly with Silicon Architects and Design Directors to review specs, optimize micro-architecture for testability/verifiability (DFV), and mitigate risk early.\nOrganizational Mentorship: Mentor Principal engineers and technical leads across the site. Champion best practices, drive technical brainstorming, and cultivate a culture of engineering excellence.\nCrisis Debugging & Escalation: Act as the ultimate technical authority for critical, complex issues that block project milestones or require deep cross-functional triage.\nRequired Qualifications & Skills\nExperience: 15+ to 17+ years of distinguished experience in ASIC/SoC Verification, having successfully guided multiple complex, large-scale tape-outs from concept to production.\nDomain Leadership: Deep, comprehensive knowledge of the networking domain, with an understanding of how system-level traffic flow impacts full-chip verification constraints.\nFull-Scale SoC Scope: Proven experience leading full SoC-level verification environments, managing top-level testbenches, and coordinating multi-subsystem integration.\nExpertise: Authoritative knowledge of System Verilog, UVM, and structural verification planning.\nInfluence & Communication: Outstanding executive communication skills. Ability to articulate complex technical risks and trade-offs clearly to both engineering teams and executive management.\nEducation: B Tech/M Tech in Electronics/Electrical Engineering, Computer Engineering, or a related field.\nPreferred / Added Advantages\nStrong, proven track record of deploying Formal Verification (FPV) at scale to displace traditional simulation.\nExperience integrating hardware emulation (e.g., Palladium, Zebu) into a unified simulation workflow.\n \n","hostedUrl":"https://jobs.lever.co/upscale-ai/9149e72d-ee97-498a-a587-3546d293afb2","applyUrl":"https://jobs.lever.co/upscale-ai/9149e72d-ee97-498a-a587-3546d293afb2/apply"},{"additionalPlain":"Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.\nEqual Opportunity\nUpscale, Inc., is building a team that reflects a wide range of perspectives, backgrounds, and experiences. We’re proud to be an Equal Opportunity Employer and consider all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, disability, or veteran status.\nAccessibility & Accommodations\nWe’re committed to making our hiring process accessible to everyone. If you need accommodations at any stage, just reach out to us at hiring@upscaleai.com—we’re happy to help. Note: This inbox is only for accommodation requests.\n","additional":"

Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.

\n

Equal Opportunity

\n

Upscale, Inc., is building a team that reflects a wide range of perspectives, backgrounds, and experiences. We’re proud to be an Equal Opportunity Employer and consider all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, disability, or veteran status.

\n

Accessibility & Accommodations

\n

We’re committed to making our hiring process accessible to everyone. If you need accommodations at any stage, just reach out to us at hiring@upscaleai.com—we’re happy to help. Note: This inbox is only for accommodation requests.

","categories":{"commitment":"Reg - Full-Time","location":"US - Headquarters","team":"AI Network Software","allLocations":["US - Headquarters"]},"createdAt":1787198300842,"descriptionPlain":"Why join Upscale, Inc. \nUpscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.\nWe focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.\nIf you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. \n\n\nAbout the role\nAI training and inference clusters live or die on the network fabric. ScaleUp builds the software that programs our high-performance Ethernet switch silicon — SDK, SAI, simulation, and the CI that keeps that stack shippable.\nWe’re looking for a DevOps engineer at the intersection of AI infrastructure, data-center networking, and silicon-aware software: reliable pipelines for an ASIC SDK, fast feedback for developers, and release paths worthy of cloud- and AI-scale deployment.\nYou’ll partner with SDK, SAI, and QA engineers, and work in GitHub + Jira day to day. Success means CI is trusted, simulation and software gates are clear, and infrastructure never blocks the next generation of AI networking features.\n","description":"

Why join Upscale, Inc. 

\n

Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

\n

We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

\n

If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. 


\n

About the role

\n

AI training and inference clusters live or die on the network fabric. ScaleUp builds the software that programs our high-performance Ethernet switch silicon — SDK, SAI, simulation, and the CI that keeps that stack shippable.

\n

We’re looking for a DevOps engineer at the intersection of AI infrastructure, data-center networking, and silicon-aware software: reliable pipelines for an ASIC SDK, fast feedback for developers, and release paths worthy of cloud- and AI-scale deployment.

\n

You’ll partner with SDK, SAI, and QA engineers, and work in GitHub + Jira day to day. Success means CI is trusted, simulation and software gates are clear, and infrastructure never blocks the next generation of AI networking features.

\n
","id":"8b9dc9b7-1031-4d69-8679-3eaa724b1f69","lists":[{"text":"Responsibility ","content":"
\n\n
  • Own CI/CD for the ScaleUp stack that powers AI/HPC Ethernet switching (build, unit/integration, gating, artifacts, release promotion).
  • \n
  • Scale pipelines across multi-repo dependencies: switch SDK, SAI adapters, shared test frameworks, and switch simulation / model targets.
  • \n
  • Improve build caching, shared runners, and nightlies so large C/C++ and Python SDK builds stay fast and predictable.
  • \n
  • Own release / promote workflows (branch policies, artifact publish, pre-gate vs post-gate steps) so SDK drops are repeatable.
  • \n
  • Shorten commit → green for teams building programmable data-plane, QoS, ACL, RoCE-era fabrics, and AI-workload traffic patterns.
  • \n
  • Add and maintain quality gates: lint, unit tests, model smoke, coverage where useful, overnight soak — high signal, low flake.
  • \n
  • Manage artifacts and caches (CI artifacts, object storage as needed) with clear retention and failure handling.
  • \n
  • Operate Linux build/test farms for C/C++ SDKs and Python harnesses (toolchains, containers, lab/sim hosts).
  • \n
  • Improve pipeline observability (dashboards, alerts, runbooks, postmortems).
  • \n
  • Secure secrets and access for GitHub Actions, artifact stores, and internal services.
  • \n
  • Partner with QA on PR / nightly / soak jobs that validate end-to-end switch behavior before customer and cloud deployments.
  • \n
  • Publish reusable pipeline templates so new ScaleUp / AI-networking repos onboard quickly.
  • \n
  • Jira: keep engineering work traceable — epics/stories/bugs for CI and infra, link PRs and releases to tickets, support sprint and release planning with SDK/SAI/QA, tighten ticket hygiene (status, components, labels) so blockers and CI debt are visible.
  • \n\n
    "},{"text":"Qualification ","content":"
    \n\n
  • Strong CI/CD experience (GitHub Actions and/or Jenkins; GitLab CI also fine) in multi-repo environments.
  • \n
  • Deep Linux fluency: shells, packaging, toolchains, debugging native builds and shared-library / SDK load paths.
  • \n
  • Automation in Python and bash; enough CMake/Make to unblock switch-SDK CI.
  • \n
  • Containers (Docker) and self-hosted or cloud runners at meaningful scale.
  • \n
  • Proven work reducing flaky tests and improving CI signal-to-noise.
  • \n
  • Hands-on Jira (or equivalent): workflows, boards, linking commits/PRs to issues, release/version fields — comfortable driving process with developers, not only “keeping the lights on.”
  • \n
  • Clear communication with hardware-adjacent software teams.
  • \n
  • Excitement about AI data centers, Ethernet fabrics, and silicon-software co-design — not only generic cloud DevOps. \n

    Nice to have

    \n\n
  • Background in networking ASICs, switch SDKs, SAI, DPDK, or NIC/SmartNIC software.
  • \n
  • Exposure to AI/ML cluster networking (GPU fabrics, RoCE/RDMA, congestion control, telemetry).
  • \n
  • Simulation / hardware-in-the-loop CI, pytest at scale, junit/Allure-style reporting.
  • \n
  • Build-cache and large-monorepo / multi-repo release patterns; backport or branch-gating workflows.
  • \n
  • Static analysis / lint gates in CI (e.g. cppcheck, language linters).
  • \n
  • IaC (Terraform/Ansible) and cloud runners (AWS/GCP).
  • \n
  • Atlassian suite beyond Jira (Confluence runbooks, Jira + GitHub automation).
  • \n
  • Release hygiene: versioning, artifacts, SBOM/signing, branch protection / merge gates.
  • \n\n

    Why ScaleUp

    \n\n
  • Your pipelines sit under real AI networking product software — not a side CRUD service.
  • \n
  • You influence how fast we ship switch SDK + SAI features that AI clusters depend on.
  • \n
  • Small team, high ownership: changes land and developers feel them the next day.
  • \n\n\n\n
    "}],"salaryRange":{"min":222000,"max":250000,"currency":"USD","interval":"per-year-salary"},"text":"Senior Staff DevOps Engineer – Scaleup","country":"US","workplaceType":"onsite","opening":"

    Why join Upscale, Inc. 

    \n

    Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

    \n

    We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

    \n

    If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. 

    ","openingPlain":"Why join Upscale, Inc. \nUpscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.\nWe focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.\nIf you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. \n","descriptionBody":"
    \n

    About the role

    \n

    AI training and inference clusters live or die on the network fabric. ScaleUp builds the software that programs our high-performance Ethernet switch silicon — SDK, SAI, simulation, and the CI that keeps that stack shippable.

    \n

    We’re looking for a DevOps engineer at the intersection of AI infrastructure, data-center networking, and silicon-aware software: reliable pipelines for an ASIC SDK, fast feedback for developers, and release paths worthy of cloud- and AI-scale deployment.

    \n

    You’ll partner with SDK, SAI, and QA engineers, and work in GitHub + Jira day to day. Success means CI is trusted, simulation and software gates are clear, and infrastructure never blocks the next generation of AI networking features.

    \n
    ","descriptionBodyPlain":"About the role\nAI training and inference clusters live or die on the network fabric. ScaleUp builds the software that programs our high-performance Ethernet switch silicon — SDK, SAI, simulation, and the CI that keeps that stack shippable.\nWe’re looking for a DevOps engineer at the intersection of AI infrastructure, data-center networking, and silicon-aware software: reliable pipelines for an ASIC SDK, fast feedback for developers, and release paths worthy of cloud- and AI-scale deployment.\nYou’ll partner with SDK, SAI, and QA engineers, and work in GitHub + Jira day to day. Success means CI is trusted, simulation and software gates are clear, and infrastructure never blocks the next generation of AI networking features.\n","hostedUrl":"https://jobs.lever.co/upscale-ai/8b9dc9b7-1031-4d69-8679-3eaa724b1f69","applyUrl":"https://jobs.lever.co/upscale-ai/8b9dc9b7-1031-4d69-8679-3eaa724b1f69/apply"},{"additionalPlain":"Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.\nEqual Opportunity\nUpscale, Inc., is building a team that reflects a wide range of perspectives, backgrounds, and experiences. We’re proud to be an Equal Opportunity Employer and consider all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, disability, or veteran status.\nAccessibility & Accommodations\nWe’re committed to making our hiring process accessible to everyone. If you need accommodations at any stage, just reach out to us at hiring@upscaleai.com—we’re happy to help. Note: This inbox is only for accommodation requests.\n","additional":"

    Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.

    \n

    Equal Opportunity

    \n

    Upscale, Inc., is building a team that reflects a wide range of perspectives, backgrounds, and experiences. We’re proud to be an Equal Opportunity Employer and consider all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, disability, or veteran status.

    \n

    Accessibility & Accommodations

    \n

    We’re committed to making our hiring process accessible to everyone. If you need accommodations at any stage, just reach out to us at hiring@upscaleai.com—we’re happy to help. Note: This inbox is only for accommodation requests.

    ","categories":{"commitment":"Reg - Full-Time","location":"US - Headquarters","team":"AI Network Software","allLocations":["US - Headquarters"]},"createdAt":1786590492328,"descriptionPlain":"Why join Upscale, Inc. \nUpscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.\nWe focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.\nIf you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. \n\n\nPosition Overview\nThis is a full-time, on-site role for a Senior Staff Platform Engineer located in Santa Clara, CA. The engineer will own end-to-end platform software development—spanning Board Support Packages (BSP), network operating systems (SONiC, FBOSS), baseboard management controller firmware (OpenBMC), and hardware diagnostic software for both platform-level and ASIC-level validation. The ideal candidate combines deep embedded systems expertise with systems-level thinking, bridging hardware and software to deliver production-grade infrastructure at scale.\nThis role spans both x86 and ARM architectures and demands fluency across the full stack—from low-level firmware and device drivers to user-space services, telemetry frameworks, and diagnostic tooling.\n","description":"

    Why join Upscale, Inc. 

    \n

    Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

    \n

    We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

    \n

    If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. 


    \n

    Position Overview

    \n

    This is a full-time, on-site role for a Senior Staff Platform Engineer located in Santa Clara, CA. The engineer will own end-to-end platform software development—spanning Board Support Packages (BSP), network operating systems (SONiC, FBOSS), baseboard management controller firmware (OpenBMC), and hardware diagnostic software for both platform-level and ASIC-level validation. The ideal candidate combines deep embedded systems expertise with systems-level thinking, bridging hardware and software to deliver production-grade infrastructure at scale.

    \n

    This role spans both x86 and ARM architectures and demands fluency across the full stack—from low-level firmware and device drivers to user-space services, telemetry frameworks, and diagnostic tooling.

    \n
    ","id":"f167f426-9373-4031-8fba-657543e2a7a5","lists":[{"text":"Responsibility ","content":"
    \n

    Platform software Design and Development: Architect and develop Linux BSP, platform drivers, and user-space services for SONiC (x86), FBOSS (x86), and OpenBMC (ARM) platforms—covering kernel/device-tree configuration, bootloader integration, DMTF-based manageability (MCTP, PLDM, Redfish), and peripheral drivers (I2C, SPI, PCIe, GPIO). Design embedded diagnostic firmware in C/C++ for hardware bring-up, manufacturing validation, and health monitoring. Develop ASIC-level tests (memory, SerDes, datapath) and platform-level diagnostic suites (PCIe, power rail, thermal, transceiver), integrating diagnostics into manufacturing flows and field RMA processes. Contribute to relevant open-source communities.

    \n

    System Performance Analysis and Troubleshooting: Use structured debug methodologies and hardware tools (JTAG, logic analyzers) to isolate hardware vs. software failures and drive root-cause resolution. Profile and optimize platform software for boot time, latency, and resource utilization.

    \n

    Hardware and Software Testing and Validation: Plan and execute HW/SW validation campaigns with defined pass/fail criteria. Build automated test infrastructure in Python and Bash for orchestration, log parsing, and CI/CD integration. Instrument code for coverage and maintain quality metrics.

    \n

    Diagnostic Tools and Methodologies Development: Build scripts and utilities (Python, Bash) for faster debug, capture, and repeatable runs; standardize trace/result workflows; and hook into validation pipelines and internal tooling as programs scale.

    \n

    Collaboration with Cross-Functional Teams: Partner with hardware, firmware/software, validation, and program teams on priorities, joint debug, and evolving diagnostic coverage for production-quality outcomes.

    \n

    Ownership of Code Quality, Performance, and Reliability: Deliver maintainable code with solid tests, reviews, and engineering practice so platform,diagnostic firmware and related software meet performance and production standards.

    \n
    "},{"text":"Qualifications","content":"
    \n
    "}],"salaryRange":{"min":237000,"max":260000,"currency":"USD","interval":"per-year-salary"},"text":"Senior Staff Engineer - Platform","country":"US","workplaceType":"onsite","opening":"

    Why join Upscale, Inc. 

    \n

    Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

    \n

    We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

    \n

    If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. 

    ","openingPlain":"Why join Upscale, Inc. \nUpscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.\nWe focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.\nIf you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. \n","descriptionBody":"
    \n

    Position Overview

    \n

    This is a full-time, on-site role for a Senior Staff Platform Engineer located in Santa Clara, CA. The engineer will own end-to-end platform software development—spanning Board Support Packages (BSP), network operating systems (SONiC, FBOSS), baseboard management controller firmware (OpenBMC), and hardware diagnostic software for both platform-level and ASIC-level validation. The ideal candidate combines deep embedded systems expertise with systems-level thinking, bridging hardware and software to deliver production-grade infrastructure at scale.

    \n

    This role spans both x86 and ARM architectures and demands fluency across the full stack—from low-level firmware and device drivers to user-space services, telemetry frameworks, and diagnostic tooling.

    \n
    ","descriptionBodyPlain":"Position Overview\nThis is a full-time, on-site role for a Senior Staff Platform Engineer located in Santa Clara, CA. The engineer will own end-to-end platform software development—spanning Board Support Packages (BSP), network operating systems (SONiC, FBOSS), baseboard management controller firmware (OpenBMC), and hardware diagnostic software for both platform-level and ASIC-level validation. The ideal candidate combines deep embedded systems expertise with systems-level thinking, bridging hardware and software to deliver production-grade infrastructure at scale.\nThis role spans both x86 and ARM architectures and demands fluency across the full stack—from low-level firmware and device drivers to user-space services, telemetry frameworks, and diagnostic tooling.\n","hostedUrl":"https://jobs.lever.co/upscale-ai/f167f426-9373-4031-8fba-657543e2a7a5","applyUrl":"https://jobs.lever.co/upscale-ai/f167f426-9373-4031-8fba-657543e2a7a5/apply"},{"additionalPlain":"Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.\nEqual Opportunity\nUpscale, Inc., is building a team that reflects a wide range of perspectives, backgrounds, and experiences. We’re proud to be an Equal Opportunity Employer and consider all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, disability, or veteran status.\nAccessibility & Accommodations\nWe’re committed to making our hiring process accessible to everyone. If you need accommodations at any stage, just reach out to us at hiring@upscaleai.com—we’re happy to help. Note: This inbox is only for accommodation requests.\n","additional":"

    Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.

    \n

    Equal Opportunity

    \n

    Upscale, Inc., is building a team that reflects a wide range of perspectives, backgrounds, and experiences. We’re proud to be an Equal Opportunity Employer and consider all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, disability, or veteran status.

    \n

    Accessibility & Accommodations

    \n

    We’re committed to making our hiring process accessible to everyone. If you need accommodations at any stage, just reach out to us at hiring@upscaleai.com—we’re happy to help. Note: This inbox is only for accommodation requests.

    ","categories":{"commitment":"Reg - Full-Time","location":"US - Headquarters","team":"IT","allLocations":["US - Headquarters"]},"createdAt":1787689688733,"descriptionPlain":"Why join Upscale, Inc. \nUpscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.\nWe focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.\nIf you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. \n\n\nJ\nRole Summary \nOwn the engineering lab ecosystem end-to-end racks, switches, and software labs - at UpscaleAI, a fast-moving AI hardware and infrastructure company. This is a hands-on role first and foremost. You're the person engineers and lab owners rely on to keep labs running, equipment tracked, networking connected, and projects on schedule, while also planning ahead and building the processes that let the operation scale as headcount and hardware volume grow quickly. \n","description":"

    Why join Upscale, Inc. 

    \n

    Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

    \n

    We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

    \n

    If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. 


    \n
    \n

    J

    \n
    \n
    \n

    Role Summary 

    \n
    \n
    \n

    Own the engineering lab ecosystem end-to-end racks, switches, and software labs - at UpscaleAI, a fast-moving AI hardware and infrastructure company. This is a hands-on role first and foremost. You're the person engineers and lab owners rely on to keep labs running, equipment tracked, networking connected, and projects on schedule, while also planning ahead and building the processes that let the operation scale as headcount and hardware volume grow quickly. 

    \n
    \n
    ","id":"2554d2af-903a-4d32-a8af-d7d5e89c041d","lists":[{"text":"Responsibilities ","content":"
    \n
    \n
    \n
    \n
    \n
    \n
    \n
    \n
    \n
    \n
    \n
    "},{"text":"","content":"
    \n
    \n
    \n
      \n
    • \n

      10 – 12 years of hands-on experience in lab operations, hardware/test infrastructure, systems administration, or data center/networking operations, ideally in a hardware, networking, or semiconductor company. 

      \n
    • \n\n
    \n
    \n
      \n
    • \n

      Bachelor's degree in a technical field or equivalent hands-on experience. 

      \n
    • \n\n
    \n
    \n
      \n
    • \n

      Demonstrated hands-on experience with servers, racks, switches, and lab equipment - this is not a desk-only management role. 

      \n
    • \n\n
    \n
    \n
      \n
    • \n

      Physically able to rack and stack hardware, move and lift equipment, and travel to or work on-site at colocation/data center facilities as required - physical hardware handling is a core, required part of this job. 

      \n
    • \n\n
    \n
    \n
      \n
    • \n

      Networking fundamentals (switches, cabling, protocols) with the ability to own connectivity and systems issues independently as part of the IT organization. 

      \n
    • \n\n
    \n
    \n
      \n
    • \n

      Proven track record working directly with lab owners and stakeholders to plan and forecast lab needs. 

      \n
    • \n\n
    \n
    \n
      \n
    • \n

      Proven inventory/asset management experience, including building tracking systems and running physical audits yourself. 

      \n
    • \n\n
    \n
    \n
      \n
    • \n

      Strong project organization skills, including managing competing priorities and requests across engineering teams. 

      \n
    • \n\n
    \n
    \n
    \n
    \n
      \n
    • \n

      Experience with lab or equipment procurement and vendor management. 

      \n
    • \n\n
    \n
    \n
      \n
    • \n

      Excellent cross-functional communication - this role sits within IT, bridging engineering, facilities, and lab owners, and requires being both a planner and a doer. 

      \n
    • \n\n
    \n
    \n

    Preferred Qualifications 

    \n
    \n
    \n
      \n
    • \n

      Experience in a networking, server, or infrastructure company. 

      \n
    • \n\n
    \n
    \n
      \n
    • \n

      Scripting/automation skills. 

      \n
    • \n\n
    \n
    \n
      \n
    • \n

      Prior experience in a similar role managing labs environment is a plus 

      \n
    • \n\n
    \n
    \n
      \n
    • \n

      Project tracking and 

      \n
    • \n\n
    \n
    \n
      \n
    • \n

       organization 

      \n
    • \n\n
    \n
    \n
    "}],"salaryRange":{"min":205000,"max":230000,"currency":"USD","interval":"per-year-salary"},"text":"Senior Staff Engineer, Lab Operations","country":"US","workplaceType":"onsite","opening":"

    Why join Upscale, Inc. 

    \n

    Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

    \n

    We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

    \n

    If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. 

    ","openingPlain":"Why join Upscale, Inc. \nUpscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.\nWe focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.\nIf you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. \n","descriptionBody":"
    \n
    \n

    J

    \n
    \n
    \n

    Role Summary 

    \n
    \n
    \n

    Own the engineering lab ecosystem end-to-end racks, switches, and software labs - at UpscaleAI, a fast-moving AI hardware and infrastructure company. This is a hands-on role first and foremost. You're the person engineers and lab owners rely on to keep labs running, equipment tracked, networking connected, and projects on schedule, while also planning ahead and building the processes that let the operation scale as headcount and hardware volume grow quickly. 

    \n
    \n
    ","descriptionBodyPlain":"J\nRole Summary \nOwn the engineering lab ecosystem end-to-end racks, switches, and software labs - at UpscaleAI, a fast-moving AI hardware and infrastructure company. This is a hands-on role first and foremost. You're the person engineers and lab owners rely on to keep labs running, equipment tracked, networking connected, and projects on schedule, while also planning ahead and building the processes that let the operation scale as headcount and hardware volume grow quickly. \n","hostedUrl":"https://jobs.lever.co/upscale-ai/2554d2af-903a-4d32-a8af-d7d5e89c041d","applyUrl":"https://jobs.lever.co/upscale-ai/2554d2af-903a-4d32-a8af-d7d5e89c041d/apply"},{"additionalPlain":"Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.\nEqual Opportunity\nUpscale, Inc., is building a team that reflects a wide range of perspectives, backgrounds, and experiences. We’re proud to be an Equal Opportunity Employer and consider all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, disability, or veteran status.\nAccessibility & Accommodations\nWe’re committed to making our hiring process accessible to everyone. If you need accommodations at any stage, just reach out to us at hiring@upscaleai.com—we’re happy to help. Note: This inbox is only for accommodation requests.\n","additional":"

    Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.

    \n

    Equal Opportunity

    \n

    Upscale, Inc., is building a team that reflects a wide range of perspectives, backgrounds, and experiences. We’re proud to be an Equal Opportunity Employer and consider all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, disability, or veteran status.

    \n

    Accessibility & Accommodations

    \n

    We’re committed to making our hiring process accessible to everyone. If you need accommodations at any stage, just reach out to us at hiring@upscaleai.com—we’re happy to help. Note: This inbox is only for accommodation requests.

    ","categories":{"commitment":"Reg - Full-Time","location":"Taiwan - Remote","team":"Operations","allLocations":["Taiwan - Remote"]},"createdAt":1787019402805,"descriptionPlain":"Why join Upscale, Inc. \nUpscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.\nWe focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.\nIf you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. \n","description":"

    Why join Upscale, Inc. 

    \n

    Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

    \n

    We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

    \n

    If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. 


    \n

    About the job

    \n

    Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Upscale AI's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

    Upscale AI’s SOCs are the most advanced in the world. In this role, you will help to manufacture the SoC’s that power these data centers by developing and deploying comprehensive manufacturing test and data analytics solutions for high-volume manufacturing at wafer fabrications and Outsourced Semiconductor Assembly and Tests (OSAT’s). You will have an opportunity to create silicon in the most advanced technologies and follow it into the field to close the loop back to design and test for the next-generation of chips. You will help to integrate SoC technologies into devices and drive manufacturing test flows to assure performance and screen devices. You will drive yield improvement, cost optimization and work closely with cross-functional teams to ensure the optimal test coverage in production to ensure high quality SoCs. You will need to have a strong understanding of Integrated Circuit (IC) flows, wafer processing, testing, qualification, diagnostics, and failure analysis. You will work with various groups to deploy screening methodologies and flows for data processing, analytics and diagnostics. You will drive the release of cost-effective production test solutions into mass production to hit yield and quality goals.

    \n
    ","id":"3f12ccd0-a6ca-4bb2-983a-63ff8606fd99","lists":[{"text":"Responsibilities","content":"
    \n
    "},{"text":"Qualifications","content":"
    \n
    "}],"salaryRange":{"min":2087802,"max":2269372,"currency":"TWD","interval":"per-year-salary"},"text":"Senior Test Engineer","country":"TW","workplaceType":"remote","opening":"

    Why join Upscale, Inc. 

    \n

    Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

    \n

    We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

    \n

    If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. 

    ","openingPlain":"Why join Upscale, Inc. \nUpscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.\nWe focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.\nIf you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. \n","descriptionBody":"
    \n

    About the job

    \n

    Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Upscale AI's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

    Upscale AI’s SOCs are the most advanced in the world. In this role, you will help to manufacture the SoC’s that power these data centers by developing and deploying comprehensive manufacturing test and data analytics solutions for high-volume manufacturing at wafer fabrications and Outsourced Semiconductor Assembly and Tests (OSAT’s). You will have an opportunity to create silicon in the most advanced technologies and follow it into the field to close the loop back to design and test for the next-generation of chips. You will help to integrate SoC technologies into devices and drive manufacturing test flows to assure performance and screen devices. You will drive yield improvement, cost optimization and work closely with cross-functional teams to ensure the optimal test coverage in production to ensure high quality SoCs. You will need to have a strong understanding of Integrated Circuit (IC) flows, wafer processing, testing, qualification, diagnostics, and failure analysis. You will work with various groups to deploy screening methodologies and flows for data processing, analytics and diagnostics. You will drive the release of cost-effective production test solutions into mass production to hit yield and quality goals.

    \n
    ","descriptionBodyPlain":"","hostedUrl":"https://jobs.lever.co/upscale-ai/3f12ccd0-a6ca-4bb2-983a-63ff8606fd99","applyUrl":"https://jobs.lever.co/upscale-ai/3f12ccd0-a6ca-4bb2-983a-63ff8606fd99/apply"},{"additionalPlain":"Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.\nEqual Opportunity\nUpscale, Inc., is building a team that reflects a wide range of perspectives, backgrounds, and experiences. We’re proud to be an Equal Opportunity Employer and consider all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, disability, or veteran status.\nAccessibility & Accommodations\nWe’re committed to making our hiring process accessible to everyone. If you need accommodations at any stage, just reach out to us at hiring@upscaleai.com—we’re happy to help. Note: This inbox is only for accommodation requests.\n","additional":"

    Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.

    \n

    Equal Opportunity

    \n

    Upscale, Inc., is building a team that reflects a wide range of perspectives, backgrounds, and experiences. We’re proud to be an Equal Opportunity Employer and consider all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, disability, or veteran status.

    \n

    Accessibility & Accommodations

    \n

    We’re committed to making our hiring process accessible to everyone. If you need accommodations at any stage, just reach out to us at hiring@upscaleai.com—we’re happy to help. Note: This inbox is only for accommodation requests.

    ","categories":{"commitment":"Reg - Full-Time","location":"Taiwan - Remote","team":"Operations","allLocations":["Taiwan - Remote"]},"createdAt":1786586895364,"descriptionPlain":"Why join Upscale, Inc. \nUpscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.\nWe focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.\nIf you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. \n","description":"

    Why join Upscale, Inc. 

    \n

    Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

    \n

    We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

    \n

    If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. 


    \n

    About the job

    \n

    The Senior Test Manager is responsible for building and maintaining a motivated and capable team, establishing an effective and consistent approach to the delivery of Test Management.

    Responsible for leading the delivery of test management to multiple CQC technology products and IT projects, working with other teams to proactively manage dependencies, overcome obstacles and get the best value against constraints.

    \n

    The Senior Test Manager oversees the testing process of products or systems to ensure they meet quality standards before release. This position involves overseeing an organization's testing framework, policy, processes and teams, requiring a strategic mindset and technical expertise.

    \n


    Upscale AI’s SOCs are the most advanced in the world. In this role, you will help to manufacture the SoC’s that power these data centers by developing and deploying comprehensive manufacturing test and data analytics solutions for high-volume manufacturing at wafer fabrications and Outsourced Semiconductor Assembly and Tests (OSAT’s).

    You will have an opportunity to create silicon in the most advanced technologies and follow it into the field to close the loop back to design and test for the next-generation of chips. You will help to integrate SoC technologies into devices and drive manufacturing test flows to assure performance and screen devices.

    You will drive yield improvement, cost optimization and work closely with cross-functional teams to ensure the optimal test coverage in production to ensure high quality SoCs. You will need to have a strong understanding of Integrated Circuit (IC) flows, wafer processing, testing, qualification, diagnostics, and failure analysis.

    You will work with various groups to deploy screening methodologies and flows for data processing, analytics and diagnostics. You will drive the release of cost-effective production test solutions into mass production to hit yield and quality goals.

    \n
    ","id":"161069b7-ec2b-4bfd-811c-2d56a07ebd75","lists":[{"text":"Responsibilities","content":"
    \n
    "},{"text":"Preferred qualifications","content":"
    \n
    "}],"salaryRange":{"min":3499214,"max":3729519,"currency":"TWD","interval":"per-year-salary"},"text":"Senior Test Manager","country":"TW","workplaceType":"remote","opening":"

    Why join Upscale, Inc. 

    \n

    Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

    \n

    We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

    \n

    If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. 

    ","openingPlain":"Why join Upscale, Inc. \nUpscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.\nWe focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.\nIf you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. \n","descriptionBody":"
    \n

    About the job

    \n

    The Senior Test Manager is responsible for building and maintaining a motivated and capable team, establishing an effective and consistent approach to the delivery of Test Management.

    Responsible for leading the delivery of test management to multiple CQC technology products and IT projects, working with other teams to proactively manage dependencies, overcome obstacles and get the best value against constraints.

    \n

    The Senior Test Manager oversees the testing process of products or systems to ensure they meet quality standards before release. This position involves overseeing an organization's testing framework, policy, processes and teams, requiring a strategic mindset and technical expertise.

    \n


    Upscale AI’s SOCs are the most advanced in the world. In this role, you will help to manufacture the SoC’s that power these data centers by developing and deploying comprehensive manufacturing test and data analytics solutions for high-volume manufacturing at wafer fabrications and Outsourced Semiconductor Assembly and Tests (OSAT’s).

    You will have an opportunity to create silicon in the most advanced technologies and follow it into the field to close the loop back to design and test for the next-generation of chips. You will help to integrate SoC technologies into devices and drive manufacturing test flows to assure performance and screen devices.

    You will drive yield improvement, cost optimization and work closely with cross-functional teams to ensure the optimal test coverage in production to ensure high quality SoCs. You will need to have a strong understanding of Integrated Circuit (IC) flows, wafer processing, testing, qualification, diagnostics, and failure analysis.

    You will work with various groups to deploy screening methodologies and flows for data processing, analytics and diagnostics. You will drive the release of cost-effective production test solutions into mass production to hit yield and quality goals.

    \n
    ","descriptionBodyPlain":"","hostedUrl":"https://jobs.lever.co/upscale-ai/161069b7-ec2b-4bfd-811c-2d56a07ebd75","applyUrl":"https://jobs.lever.co/upscale-ai/161069b7-ec2b-4bfd-811c-2d56a07ebd75/apply"},{"additionalPlain":"Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.\nEqual Opportunity\nUpscale, Inc., is building a team that reflects a wide range of perspectives, backgrounds, and experiences. We’re proud to be an Equal Opportunity Employer and consider all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, disability, or veteran status.\nAccessibility & Accommodations\nWe’re committed to making our hiring process accessible to everyone. If you need accommodations at any stage, just reach out to us at hiring@upscaleai.com—we’re happy to help. Note: This inbox is only for accommodation requests.\n","additional":"

    Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.

    \n

    Equal Opportunity

    \n

    Upscale, Inc., is building a team that reflects a wide range of perspectives, backgrounds, and experiences. We’re proud to be an Equal Opportunity Employer and consider all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, disability, or veteran status.

    \n

    Accessibility & Accommodations

    \n

    We’re committed to making our hiring process accessible to everyone. If you need accommodations at any stage, just reach out to us at hiring@upscaleai.com—we’re happy to help. Note: This inbox is only for accommodation requests.

    ","categories":{"commitment":"Reg - Full-Time","location":"US - Headquarters","team":"Hardware Engineering","allLocations":["US - Headquarters"]},"createdAt":1782093479396,"descriptionPlain":"Why join Upscale, Inc. \nUpscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.\nWe focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.\nIf you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. \n","description":"

    Why join Upscale, Inc. 

    \n

    Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

    \n

    We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

    \n

    If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. 


    Position Summary

    We are looking for a motivated Junior Signal Integrity Engineer to join our Hardware Engineering team. The candidate will support Signal Integrity (SI) and Power Integrity (PI) analysis for high-speed PCB designs used in networking, AI, data center, and compute platforms. This role offers an excellent opportunity to work alongside experienced SI engineers while developing expertise in high-speed system design, simulation, measurement, and debugging.
    ","id":"33ce81c4-8eb7-4170-b7ec-0f86e209e7d8","lists":[{"text":"Responsibilities","content":"
    \n

    Support SI/PI analysis for high-speed PCB designs from architecture through product validation.
    Assist with channel modeling, simulation, and optimization for high-speed interfaces.
    Perform signal quality measurements using laboratory equipment.
    Support PCB stackup reviews, routing reviews, and design guideline development.
    Analyze transmission lines, vias, connectors, cables, and package-to-board interfaces.
    Participate in correlation between simulation and laboratory measurements.
    Work closely with PCB designers, hardware engineers, package engineers, and silicon teams.
    Document simulation results, measurements, and design recommendations.
    Assist in root-cause analysis and debugging of signal integrity issues.

    \n

    Preferred Qualifications

    BS or MS in Electrical Engineering or related field.
    0–3 years of experience in Signal Integrity, PCB Design, Hardware Design, or related areas.
    Basic understanding of:
    - High-speed digital design
    - Transmission line theory
    - PCB stackups and routing
    - S-parameters and eye diagrams
    - SI and PI fundamentals

    \n

    Exposure to one or more simulation tools such as: 

    Cadence Clarity
    Cadence Sigrity
    Keysight ADS
    Ansys HFSS

    \n

    Exposure to laboratory instruments such as: 

    Vector Network Analyzer (VNA)
    TDR/TDT
    High-speed Oscilloscopes
    Strong analytical and problem-solving skills.
    Excellent communication and teamwork abilities.

    \n

    Nice to Have 

    Experience with 56G/112G/224G SerDes systems.
    Knowledge of PCIe, Ethernet, UCIe, DDR interfaces

    \n
    "}],"salaryRange":{"min":117000,"max":129000,"currency":"USD","interval":"per-year-salary"},"text":"Signal Integrity Engineer I","country":"US","workplaceType":"onsite","opening":"

    Why join Upscale, Inc. 

    \n

    Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

    \n

    We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

    \n

    If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. 

    ","openingPlain":"Why join Upscale, Inc. \nUpscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.\nWe focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.\nIf you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. \n","descriptionBody":"
    Position Summary

    We are looking for a motivated Junior Signal Integrity Engineer to join our Hardware Engineering team. The candidate will support Signal Integrity (SI) and Power Integrity (PI) analysis for high-speed PCB designs used in networking, AI, data center, and compute platforms. This role offers an excellent opportunity to work alongside experienced SI engineers while developing expertise in high-speed system design, simulation, measurement, and debugging.
    ","descriptionBodyPlain":"","hostedUrl":"https://jobs.lever.co/upscale-ai/33ce81c4-8eb7-4170-b7ec-0f86e209e7d8","applyUrl":"https://jobs.lever.co/upscale-ai/33ce81c4-8eb7-4170-b7ec-0f86e209e7d8/apply"},{"additionalPlain":"Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.\nEqual Opportunity\nUpscale, Inc., is building a team that reflects a wide range of perspectives, backgrounds, and experiences. We’re proud to be an Equal Opportunity Employer and consider all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, disability, or veteran status.\nAccessibility & Accommodations\nWe’re committed to making our hiring process accessible to everyone. If you need accommodations at any stage, just reach out to us at hiring@upscaleai.com—we’re happy to help. Note: This inbox is only for accommodation requests.\n","additional":"

    Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.

    \n

    Equal Opportunity

    \n

    Upscale, Inc., is building a team that reflects a wide range of perspectives, backgrounds, and experiences. We’re proud to be an Equal Opportunity Employer and consider all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, disability, or veteran status.

    \n

    Accessibility & Accommodations

    \n

    We’re committed to making our hiring process accessible to everyone. If you need accommodations at any stage, just reach out to us at hiring@upscaleai.com—we’re happy to help. Note: This inbox is only for accommodation requests.

    ","categories":{"commitment":"Reg - Full-Time","location":"US - Headquarters","team":"Hardware Engineering","allLocations":["US - Headquarters"]},"createdAt":1782096130051,"descriptionPlain":"Why join Upscale, Inc. \nUpscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.\nWe focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.\nIf you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. \n","description":"

    Why join Upscale, Inc. 

    \n

    Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

    \n

    We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

    \n

    If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. 


    Position Summary

    We are seeking an experienced Senior Signal Integrity Engineer to lead SI/PI design and validation activities for next-generation high-speed networking, AI, and data center products. The ideal candidate will have deep expertise in high-speed PCB design, simulation, measurement, and correlation across complex systems operating at 112G and 224G data rates.
    ","id":"8ef66006-75c8-4294-976e-fadc98af0bee","lists":[{"text":"Responsibilities","content":"
    \n

    - Lead Signal Integrity and Power Integrity analysis for complex PCB and system designs.
    - Define SI/PI architecture, design rules, and channel budgets for high-speed interfaces.
    - Perform detailed channel simulations and optimization using industry-standard tools.
    - Drive correlation between simulation and laboratory measurements.
    - Develop and validate models for packages, PCBs, connectors, cables, and complete channels.
    - Conduct pre-layout and post-layout SI/PI analysis.
    - Perform compliance and interoperability analysis for industry standards.
    - Debug complex signal integrity issues and drive root-cause resolution.
    - Define PCB stackups, routing requirements, via structures, and return path strategies.
    - Mentor junior engineers and provide technical leadership across projects.
    - Collaborate with silicon, package, board, mechanical, and manufacturing teams.
    - Interface with vendors and customers on SI/PI-related technical topics.

    \n

    Required Qualifications:

    - BS/MS in Electrical Engineering or related field.
    - 5+ years of experience in Signal Integrity, High-Speed Design, or related areas.

    \n

    Strong understanding of: 

    - Signal Integrity and Power Integrity principles
    - Electromagnetic theory
    - Transmission line analysis
    - High-speed SerDes architectures
    - PCB and package design
    - Channel compliance methodologies

    \n

    Extensive hands-on experience with: 

    - Ansys HFSS
    - Cadence Clarity
    - Cadence Sigrity
    - Keysight ADS

    Strong laboratory experience with: 

    - Vector Network Analyzer (VNA)
    - TDR/TDT systems
    - High-bandwidth oscilloscopes
    - De-embedding and calibration techniques

    Experience analyzing: 

    PCB channels, Connectors, Cables, Packages, Backplanes and midplanes
    Ability to correlate simulations with measured results and drive design improvements.

    \n

    Preferred Qualifications: 

    - Experience with 112G/224G PAM4 SerDes systems.
    - Experience with Ethernet, PCIe, UCIe, CXL, DDR, or AI networking products.
    - Knowledge of COM, ERL, eye analysis, jitter decomposition, and channel compliance methodologies.
    - Experience with Python, MATLAB, or automation frameworks.
    - Experience leading SI strategy for large-scale hardware programs.

    \n

    Desired Attributes: 

    - Strong technical leadership and mentoring skills.
    - Excellent cross-functional communication.
    - Ability to drive projects independently from concept through production.
    - Customer-facing and vendor collaboration experience.
    - Passion for solving challenging high-speed design pro

    \n
    "}],"salaryRange":{"min":159000,"currency":"USD","interval":"per-year-salary","max":170000},"text":"Signal Integrity Senior Engineer","country":"US","workplaceType":"onsite","opening":"

    Why join Upscale, Inc. 

    \n

    Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

    \n

    We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

    \n

    If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. 

    ","openingPlain":"Why join Upscale, Inc. \nUpscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.\nWe focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.\nIf you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. \n","descriptionBody":"
    Position Summary

    We are seeking an experienced Senior Signal Integrity Engineer to lead SI/PI design and validation activities for next-generation high-speed networking, AI, and data center products. The ideal candidate will have deep expertise in high-speed PCB design, simulation, measurement, and correlation across complex systems operating at 112G and 224G data rates.
    ","descriptionBodyPlain":"","hostedUrl":"https://jobs.lever.co/upscale-ai/8ef66006-75c8-4294-976e-fadc98af0bee","applyUrl":"https://jobs.lever.co/upscale-ai/8ef66006-75c8-4294-976e-fadc98af0bee/apply"},{"additionalPlain":"Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.\nEqual Opportunity\nUpscale, Inc., is building a team that reflects a wide range of perspectives, backgrounds, and experiences. We’re proud to be an Equal Opportunity Employer and consider all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, disability, or veteran status.\nAccessibility & Accommodations\nWe’re committed to making our hiring process accessible to everyone. If you need accommodations at any stage, just reach out to us at hiring@upscaleai.com—we’re happy to help. Note: This inbox is only for accommodation requests.\n","additional":"

    Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.

    \n

    Equal Opportunity

    \n

    Upscale, Inc., is building a team that reflects a wide range of perspectives, backgrounds, and experiences. We’re proud to be an Equal Opportunity Employer and consider all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, disability, or veteran status.

    \n

    Accessibility & Accommodations

    \n

    We’re committed to making our hiring process accessible to everyone. If you need accommodations at any stage, just reach out to us at hiring@upscaleai.com—we’re happy to help. Note: This inbox is only for accommodation requests.

    ","categories":{"commitment":"Reg - Full-Time","location":"US - Headquarters","team":"Product Support","allLocations":["US - Headquarters"]},"createdAt":1784687061525,"descriptionPlain":"Why join Upscale, Inc. \nUpscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.\nWe focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.\nIf you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. \n","description":"

    Why join Upscale, Inc. 

    \n

    Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

    \n

    We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

    \n

    If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. 


    \n

    Role Overview

    \n

    We are looking for a Technical Support Lead Engineer with 12+ years of experience who is passionate about building reliable networking switches and solving challenging infrastructure problems.

    \n

    Own end-to-end network bring-up and performance for GPU AI clusters during customer PoCs. You’ll be the leader for switching ASIC pipeline tuning, platform readiness, and fabric performance (Ethernet/RoCEv2 and/or InfiniBand), turning requirements into reproducible configurations that hit utilization and tail-latency targets at scale.

    \n

    As part of the AI Networking team, you'll debug software, develop automation, validate networking platforms, troubleshoot complex system issues, and work closely with engineering teams and customers to ensure the best customer experience. You'll have the opportunity to work on technologies powering next-generation GPU clusters and AI data centers while learning from experienced engineers in a fast-paced startup environment.

    \n
    ","id":"e76c35a5-b57f-4653-a4ee-3ea65ce7e944","lists":[{"text":"Responsibilities","content":"
    \n

    Design, develop, and maintain features and enhancements for the SONiC NOS platform.

    \n

    · Debug, troubleshoot, and resolve issues on SONiC platforms.

    \n

    · Develop and execute debugging and troubleshoot infrastructure.

    \n

    · Collaborate closely with cross-functional teams including hardware engineers and Test teams.

    \n

    · Participate in code reviews, architecture discussions, and documentation efforts.

    \n

    · Develop support strategies to root-cause Networking ASICs and Networking Systems issues.

    \n

    · Develop debugging tools, for Traffic monitoring and Performance measurements.

    \n

    · Debug issues across software, Linux systems, networking stacks, and distributed infrastructure.

    \n

    · Be a point of contact for customer deployments, integration testing, proof-of-concepts, and field issue resolution.

    \n

    · Build tools that improve deployment efficiency, observability, telemetry, and automated testing.

    \n

    · Collaborate with software, infrastructure, QA, and product teams to identify root causes and deliver robust solutions.

    \n

    · Contribute to backend services, APIs, orchestration components, and infrastructure automation.

    \n

    · Document technical findings and communicate effectively with engineering teams and customers.

    \n
    "},{"text":"Qualifications","content":"
    \n

    Required Qualifications

    \n

    · Bachelor’s or master’s degree in computer science, Electrical Engineering, or a related field.

    \n

    · Minimum of 12 years of work experience is required, with at least 3 years of hands-on SONiC or equivalent Network Operating System (NOS) development experience preferred.

    \n

    · Strong programming skills in Python, Go, or a similar language.

    \n

    · Solid understanding of Linux, TCP/IP networking, routing, switching, VLANs, and network troubleshooting.

    \n

    · Experience with PTF (Packet Test Framework) and SPyTest for network validation.

    \n

    · Familiarity with Linux internals, docker containers.

    \n

    · Excellent problem-solving skills and ability to work in a fast-paced, collaborative environment.

    \n

    · Knowledge of network ASICs and switch hardware architecture is mandatory.

    \n

    · Excellent written and verbal communication skills.

    \n

    · Ability to thrive in a collaborative, fast-paced startup environment with a strong sense of ownership.

    \n


    Preferred Qualifications

    \n

    · Data-center networking with hands-on switch ASIC tuning and platform bring-up.

    \n

    · Proven RoCEv2 deployments at 200/400/800 G: ECN/PFC design, DCQCN tuning, DSCP/PCP mapping, queue/WRR shaping.

    \n

    · Deep buffer/queueing knowledge (headroom, xon/xoff, dynamic thresholds, VOQ vs shared pools).

    \n

    · SONiC (buffers.json, qos.json, pfcwd, ecn), Enterprise-OS (class-map/type qos & network-qos, policy-map, queuing).

    \n

    · Optics & PHY: PAM4 signal integrity, FEC modes, DOM/RS-FEC counters, AN/LT quirks, DAC/AOC selection.

    \n

    · Tooling: ethtool, devlink, mlnx_qos, perfquery, switch telemetry (INT/sFlow/ERSPAN), gNMI/REST, Prometheus.

    \n

    · Benchmarking: perftest, nccl-tests, iPerf3, traffic generators; reading queue stats, ECN marks, and CNP behavior.

    \n

    · EVPN/VXLAN leaf-spine for AI pods; flowlet or latency-aware hashing.

    \n

    · BlueField DPU offloads, GPUDirect RDMA; NIC QoS (DSCP-to-TC, PFCx, GEARBOX/FW).

    \n

    · Storage fabrics for AI (NFS-RDMA, NVMe-oF) and their QoS interactions.

    \n

    · Python/Ansible for templated ASIC profiles; Git workflows for config promotion.

    \n
    "}],"salaryRange":{"min":248000,"max":269000,"currency":"USD","interval":"per-year-salary"},"text":"Technical Support Principal Engineer – AI Network","country":"US","workplaceType":"onsite","opening":"

    Why join Upscale, Inc. 

    \n

    Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

    \n

    We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

    \n

    If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. 

    ","openingPlain":"Why join Upscale, Inc. \nUpscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $300M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.\nWe focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.\nIf you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. \n","descriptionBody":"
    \n

    Role Overview

    \n

    We are looking for a Technical Support Lead Engineer with 12+ years of experience who is passionate about building reliable networking switches and solving challenging infrastructure problems.

    \n

    Own end-to-end network bring-up and performance for GPU AI clusters during customer PoCs. You’ll be the leader for switching ASIC pipeline tuning, platform readiness, and fabric performance (Ethernet/RoCEv2 and/or InfiniBand), turning requirements into reproducible configurations that hit utilization and tail-latency targets at scale.

    \n

    As part of the AI Networking team, you'll debug software, develop automation, validate networking platforms, troubleshoot complex system issues, and work closely with engineering teams and customers to ensure the best customer experience. You'll have the opportunity to work on technologies powering next-generation GPU clusters and AI data centers while learning from experienced engineers in a fast-paced startup environment.

    \n
    ","descriptionBodyPlain":"","hostedUrl":"https://jobs.lever.co/upscale-ai/e76c35a5-b57f-4653-a4ee-3ea65ce7e944","applyUrl":"https://jobs.lever.co/upscale-ai/e76c35a5-b57f-4653-a4ee-3ea65ce7e944/apply"}]