Who we are:
We are a startup building foundational technology to address performance, scalability, and resiliency challenges in large-scale AI data center clusters. We are backed by top-tier VC firms and notable angel investors.
The company is led by experienced builders and operators who have founded companies, taken them to scale, and exited successfully. We work with a strong sense of unity and shared responsibility, and we expect trust, integrity, and respect in how we collaborate and make decisions. We hold ourselves accountable to one another and to the quality of the work we deliver.
Headquartered in Silicon Valley, we operate across a mix of remote and on-site locations in the U.S. and Canada. We aim to create an environment where people are treated fairly, supported in their growth, and are empowered to do meaningful work alongside others who take the craft seriously.
What we need
This is a place to share your resume for any potential needs that are not featured on our page.
Agency Note:
We do not accept resumes from agencies or search firms. Please do not forward candidate profiles through our careers page, email, LinkedIn messages, or directly to company employees. Any resumes submitted will be deemed the property of the company, and no fees will be paid in the event the candidate is hired.
","descriptionPlain":"Who we are:\n\nWe are a startup building foundational technology to address performance, scalability, and resiliency challenges in large-scale AI data center clusters. We are backed by top-tier VC firms and notable angel investors.\n\nThe company is led by experienced builders and operators who have founded companies, taken them to scale, and exited successfully. We work with a strong sense of unity and shared responsibility, and we expect trust, integrity, and respect in how we collaborate and make decisions. We hold ourselves accountable to one another and to the quality of the work we deliver.\n\nHeadquartered in Silicon Valley, we operate across a mix of remote and on-site locations in the U.S. and Canada. We aim to create an environment where people are treated fairly, supported in their growth, and are empowered to do meaningful work alongside others who take the craft seriously.\n\n\n\nWhat we need\n\nThis is a place to share your resume for any potential needs that are not featured on our page.\n\n\n\nAgency Note:\n\nWe do not accept resumes from agencies or search firms. Please do not forward candidate profiles through our careers page, email, LinkedIn messages, or directly to company employees. Any resumes submitted will be deemed the property of the company, and no fees will be paid in the event the candidate is hired."},{"id":"eff63ac7-852b-4439-9c71-8def92b1b709","title":"System Software Engineer - AI","department":"Software","team":"Software","employmentType":"FullTime","location":"Palo Alto","secondaryLocations":[],"publishedAt":"2026-07-21T23:30:21.038+00:00","isListed":true,"isRemote":true,"workplaceType":"Hybrid","address":{"postalAddress":{"postalCode":"94306","addressRegion":"California","streetAddress":"2175 Park Blvd","addressCountry":"United States","addressLocality":"Palo Alto"}},"jobUrl":"https://jobs.ashbyhq.com/delos-data/eff63ac7-852b-4439-9c71-8def92b1b709","applyUrl":"https://jobs.ashbyhq.com/delos-data/eff63ac7-852b-4439-9c71-8def92b1b709/application","descriptionHtml":"System Software Engineer - AI
About us:
We are a startup building foundational technology to address performance, scalability, and resiliency challenges in large-scale AI data center clusters. We are backed by top-tier VC firms and notable angel investors.
The company is led by experienced builders and operators who have founded companies, taken them to scale, and exited successfully. We work with a strong sense of unity and shared responsibility, and we expect trust, integrity, and respect in how we collaborate and make decisions. We hold ourselves accountable to one another and to the quality of the work we deliver.
Headquartered in Silicon Valley, we operate across a mix of remote and on-site locations in the U.S. and Canada. We aim to create an environment where people are treated fairly, supported in their growth, and are empowered to do meaningful work alongside others who take the craft seriously.
Some Recent Press:
https://www.eetimes.com/startup-boosts-scale-up-to-1000-gpus-in-a-single-domain/
We are looking for:
We are looking for a talented System Software Engineer to help us redefine the infrastructure layer of AI. In this role, you will bridge the gap between high-level AI frameworks and low-level system software. You will be responsible for designing and implementing the communication and execution primitives that allow large-scale AI models to run efficiently across thousands of GPUs. We are looking for a \"builder\" who thrives in the early stages of a product’s lifecycle and is passionate about solving the \"hard\" systems problems of the generative AI era.
Key Responsibilities:
Collaborate across the stack to influence the design of our foundational technology, ensuring it meets the needs of next-generation AI models.
Identify and resolve performance bottlenecks in distributed training and inference workloads through deep-dive analysis of the software-hardware interface.
Conduct rigorous performance benchmarking and characterization on multi-node clusters.
Required Skills and Qualifications:
Strong proficiency in C++ and Python, with a deep understanding of systems programming fundamentals (memory management, concurrency, OS internals).
Proficient in a Linux development environment.
Desired Skills:
Experience with GPU programming (CUDA) and performance optimization for parallel architectures.
Familiarity with distributed AI frameworks (PyTorch, JAX, or DeepSpeed) and/or inference engines (vLLM, SGLang, Dynamo/TRT-LLM).
Hands-on experience with large-scale cluster orchestration and telemetry tools.
Education:
Bachelor's or Master's degree in Computer Engineering, Computer Science, or a related field.
Location:
This is a hybrid role based in Palo Alto or Charlottesville, VA.
Compensation:
Target base salary for this role is $140,000 - $200,000 per year + meaningful equity + benefits + 401k. Our salary ranges are determined by role, level, experience, and location.
We are an equal opportunity employer. We value a range of perspectives and experiences and make employment decisions based on merit and business needs. We do not discriminate on the basis of legally protected characteristics.
Agency Note:
We do not accept resumes from agencies or search firms. Please do not forward candidate profiles through our careers page, email, LinkedIn messages, or directly to company employees. Any resumes submitted will be deemed the property of the company, and no fees will be paid in the event the candidate is hired.
#LI-EW1
","descriptionPlain":"System Software Engineer - AI\n\n\n\nAbout us:\n\nWe are a startup building foundational technology to address performance, scalability, and resiliency challenges in large-scale AI data center clusters. We are backed by top-tier VC firms and notable angel investors.\n\nThe company is led by experienced builders and operators who have founded companies, taken them to scale, and exited successfully. We work with a strong sense of unity and shared responsibility, and we expect trust, integrity, and respect in how we collaborate and make decisions. We hold ourselves accountable to one another and to the quality of the work we deliver.\n\nHeadquartered in Silicon Valley, we operate across a mix of remote and on-site locations in the U.S. and Canada. We aim to create an environment where people are treated fairly, supported in their growth, and are empowered to do meaningful work alongside others who take the craft seriously.\n\nSome Recent Press: \n\nhttps://www.eetimes.com/startup-boosts-scale-up-to-1000-gpus-in-a-single-domain/\n\n\n\nWe are looking for:\n\nWe are looking for a talented System Software Engineer to help us redefine the infrastructure layer of AI. In this role, you will bridge the gap between high-level AI frameworks and low-level system software. You will be responsible for designing and implementing the communication and execution primitives that allow large-scale AI models to run efficiently across thousands of GPUs. We are looking for a \"builder\" who thrives in the early stages of a product’s lifecycle and is passionate about solving the \"hard\" systems problems of the generative AI era.\n\n\n\nKey Responsibilities:\n\n - Collaborate across the stack to influence the design of our foundational technology, ensuring it meets the needs of next-generation AI models.\n\n - Identify and resolve performance bottlenecks in distributed training and inference workloads through deep-dive analysis of the software-hardware interface.\n\n - Conduct rigorous performance benchmarking and characterization on multi-node clusters.\n \n \n\nRequired Skills and Qualifications:\n\n - Strong proficiency in C++ and Python, with a deep understanding of systems programming fundamentals (memory management, concurrency, OS internals).\n\n - Proficient in a Linux development environment.\n \n \n\nDesired Skills:\n\n - Experience with GPU programming (CUDA) and performance optimization for parallel architectures.\n\n - Familiarity with distributed AI frameworks (PyTorch, JAX, or DeepSpeed) and/or inference engines (vLLM, SGLang, Dynamo/TRT-LLM).\n\n - Hands-on experience with large-scale cluster orchestration and telemetry tools.\n \n \n\nEducation:\n\n - Bachelor's or Master's degree in Computer Engineering, Computer Science, or a related field.\n\nLocation:\n\nThis is a hybrid role based in Palo Alto or Charlottesville, VA.\n\nCompensation:\n\nTarget base salary for this role is $140,000 - $200,000 per year + meaningful equity + benefits + 401k. Our salary ranges are determined by role, level, experience, and location.\n\nWe are an equal opportunity employer. We value a range of perspectives and experiences and make employment decisions based on merit and business needs. We do not discriminate on the basis of legally protected characteristics.\n\nAgency Note:\n\nWe do not accept resumes from agencies or search firms. Please do not forward candidate profiles through our careers page, email, LinkedIn messages, or directly to company employees. Any resumes submitted will be deemed the property of the company, and no fees will be paid in the event the candidate is hired.\n\n#LI-EW1"},{"id":"6b8a19b2-4d3b-4e2f-a413-1e48ca78ad96","title":"Software Development Engineer in Test - AI","department":"Software","team":"Software","employmentType":"FullTime","location":"Charlottesville","secondaryLocations":[],"publishedAt":"2026-08-31T22:12:45.828+00:00","isListed":true,"isRemote":true,"workplaceType":"Hybrid","address":{"postalAddress":{"addressRegion":"Virginia","addressCountry":"United States","addressLocality":"Charlottesville"}},"jobUrl":"https://jobs.ashbyhq.com/delos-data/6b8a19b2-4d3b-4e2f-a413-1e48ca78ad96","applyUrl":"https://jobs.ashbyhq.com/delos-data/6b8a19b2-4d3b-4e2f-a413-1e48ca78ad96/application","descriptionHtml":"We are a startup building foundational technology to address performance, scalability, and resiliency challenges in large-scale AI data center clusters. We are backed by top-tier VC firms and notable angel investors.
The company is led by experienced builders and operators who have founded companies, taken them to scale, and exited successfully. We work with a strong sense of unity and shared responsibility, and we expect trust, integrity, and respect in how we collaborate and make decisions. We hold ourselves accountable to one another and to the quality of the work we deliver.
Headquartered in Silicon Valley, we operate across a mix of remote and on-site locations in the U.S. and Canada. We aim to create an environment where people are treated fairly, supported in their growth, and are empowered to do meaningful work alongside others who take the craft seriously.
Some Recent Press: https://www.eetimes.com/startup-boosts-scale-up-to-1000-gpus-in-a-single-domain/
We are looking for:
We are looking for a Software Development Engineer in Test (SDET) to ensure the reliability and performance of our core AI infrastructure. In this role, you are an engineer who builds sophisticated automation frameworks and stress-testing suites to break and then harden our system.
You will be responsible for validating the intersection of distributed systems, GPU kernels, and AI frameworks. You will build a scalable foundation of trust in our code, ensuring that our performance-critical primitives work every time, at any scale.
Key Responsibilities:
Design, develop, and maintain a robust automated testing framework from the ground up that supports distributed AI training and inference workloads.
Develop complex test plans that go beyond unit tests, focusing on end-to-end system integration, stress testing, and hardware-software boundary conditions.
Partner closely with System Engineers to debug deep-seated issues in distributed clusters, using telemetry and profiling tools to identify bottlenecks.
Required Skills and Qualifications:
Strong proficiency in Python (for automation and orchestration).
Proven experience building or extending test automation frameworks for complex back-end systems.
Proven ability to troubleshoot automated test failures within complex large-scale distributed systems, and identify root causes.
Experience with containerization (Docker/Kubernetes) and modern CI/CD tools (GitHub Actions, GitLab CI, or Jenkins).
Desired Skills:
Experience with Kubernetes or Terraform or Ansible for managing test-bed environments.
Experience testing high-performance networking protocols or distributed file systems.
Experience testing software that interacts directly with drivers or firmware.
Education:
Bachelor's or Master's degree in Computer Engineering, Computer Science, or a related field.
Location:
This is a hybrid role based in Palo Alto or Charlottesville, VA.
Compensation:
Target base salary for this role is $140,000 - $200,000 per year + meaningful equity + benefits + 401k. Our salary ranges are determined by role, level, experience, and location.
We are an equal opportunity employer. We value a range of perspectives and experiences and make employment decisions based on merit and business needs. We do not discriminate on the basis of legally protected characteristics.
Agency Note:
We do not accept resumes from agencies or search firms. Please do not forward candidate profiles through our careers page, email, LinkedIn messages, or directly to company employees. Any resumes submitted will be deemed the property of the company, and no fees will be paid in the event the candidate is hired.
","descriptionPlain":"We are a startup building foundational technology to address performance, scalability, and resiliency challenges in large-scale AI data center clusters. We are backed by top-tier VC firms and notable angel investors.\n\nThe company is led by experienced builders and operators who have founded companies, taken them to scale, and exited successfully. We work with a strong sense of unity and shared responsibility, and we expect trust, integrity, and respect in how we collaborate and make decisions. We hold ourselves accountable to one another and to the quality of the work we deliver.\n\nHeadquartered in Silicon Valley, we operate across a mix of remote and on-site locations in the U.S. and Canada. We aim to create an environment where people are treated fairly, supported in their growth, and are empowered to do meaningful work alongside others who take the craft seriously.\n\nSome Recent Press: https://www.eetimes.com/startup-boosts-scale-up-to-1000-gpus-in-a-single-domain/\n\nWe are looking for:\n\nWe are looking for a Software Development Engineer in Test (SDET) to ensure the reliability and performance of our core AI infrastructure. In this role, you are an engineer who builds sophisticated automation frameworks and stress-testing suites to break and then harden our system.\n\nYou will be responsible for validating the intersection of distributed systems, GPU kernels, and AI frameworks. You will build a scalable foundation of trust in our code, ensuring that our performance-critical primitives work every time, at any scale.\n\n \n\nKey Responsibilities:\n\n - Design, develop, and maintain a robust automated testing framework from the ground up that supports distributed AI training and inference workloads.\n\n - Develop complex test plans that go beyond unit tests, focusing on end-to-end system integration, stress testing, and hardware-software boundary conditions.\n\n - Partner closely with System Engineers to debug deep-seated issues in distributed clusters, using telemetry and profiling tools to identify bottlenecks.\n \n \n\nRequired Skills and Qualifications:\n\n - Strong proficiency in Python (for automation and orchestration).\n\n - Proven experience building or extending test automation frameworks for complex back-end systems.\n\n - Proven ability to troubleshoot automated test failures within complex large-scale distributed systems, and identify root causes.\n\n - Experience with containerization (Docker/Kubernetes) and modern CI/CD tools (GitHub Actions, GitLab CI, or Jenkins).\n \n \n\nDesired Skills:\n\n - Experience with Kubernetes or Terraform or Ansible for managing test-bed environments.\n\n - Experience testing high-performance networking protocols or distributed file systems.\n\n - Experience testing software that interacts directly with drivers or firmware.\n \n \n\nEducation:\n\n - Bachelor's or Master's degree in Computer Engineering, Computer Science, or a related field.\n\nLocation:\n\nThis is a hybrid role based in Palo Alto or Charlottesville, VA.\n\nCompensation:\n\nTarget base salary for this role is $140,000 - $200,000 per year + meaningful equity + benefits + 401k. Our salary ranges are determined by role, level, experience, and location.\n\nWe are an equal opportunity employer. We value a range of perspectives and experiences and make employment decisions based on merit and business needs. We do not discriminate on the basis of legally protected characteristics.\n\nAgency Note:\n\nWe do not accept resumes from agencies or search firms. Please do not forward candidate profiles through our careers page, email, LinkedIn messages, or directly to company employees. Any resumes submitted will be deemed the property of the company, and no fees will be paid in the event the candidate is hired."},{"id":"7fbefc49-7488-4593-bbbf-d4d6e12e7363","title":"Principal AMS Design","department":"Hardware","team":"Hardware","employmentType":"FullTime","location":"Taiwan","secondaryLocations":[],"publishedAt":"2026-09-14T20:55:22.801+00:00","isListed":true,"isRemote":null,"workplaceType":null,"address":{"postalAddress":{"addressRegion":"Taiwan","addressCountry":"Taiwan","addressLocality":"Hsinchu"}},"jobUrl":"https://jobs.ashbyhq.com/delos-data/7fbefc49-7488-4593-bbbf-d4d6e12e7363","applyUrl":"https://jobs.ashbyhq.com/delos-data/7fbefc49-7488-4593-bbbf-d4d6e12e7363/application","descriptionHtml":"Principal AMS Engineer - Taiwan
Who we are:
We are a startup building foundational technology to address performance, scalability, and resiliency challenges in large-scale AI data center clusters. We are backed by top-tier VC firms and notable angel investors.
The company is led by experienced builders and operators who have founded companies, taken them to scale, and exited successfully. We work with a strong sense of unity and shared responsibility, and we expect trust, integrity, and respect in how we collaborate and make decisions. We hold ourselves accountable to one another and to the quality of the work we deliver.
Headquartered in Silicon Valley, we operate across a mix of remote and on-site locations in the U.S. and Canada. We aim to create an environment where people are treated fairly, supported in their growth, and are empowered to do meaningful work alongside others who take the craft seriously.
What we need:
We are looking for a Principal AMS Engineer to help architect, design, integrate, and validate the high-speed analog and mixed-signal technologies at the core of our products.
This is a highly technical, hands-on role spanning AMS/PHY architecture, circuit design, SoC integration, high-speed interfaces, clocking, power, package and board interaction, and silicon validation. You will work across the full development lifecycle—from early architecture and IP definition through implementation, tapeout, bring-up, and mass production.
The right person is comfortable operating beyond an individual circuit block. You understand how PHY, analog, digital, package, PCB, power, timing, and system-level considerations interact and can drive solutions across those boundaries.
Key Responsibilities:
Architect and develop analog and mixed-signal circuits and subsystems for next-generation high-speed interfaces and SoCs.
Lead architecture and integration of high-speed PHY technologies, including die-to-die, UCIe-class interfaces, DDR, HBM, and related SerDes/PHY functions.
Guide development of critical AMS functions including clocking, reference circuits, DLL/PLL-related functions, voltage monitoring, calibration, data-path circuitry, and other custom analog IP.
Drive chip/package/PCB co-design for high-speed signal and power integrity.
Own AMS for PHY integration into complex SoCs, including interface definition, floorplanning, clocking, timing, power intent, IO, and physical implementation considerations.
Partner closely with digital design, verification, physical design, package, systems, and software teams to resolve cross-domain design issues.
Develop and improve methodologies for signal integrity, power integrity, timing, low-power design, and system-level analysis.
Define requirements and evaluate internal and third-party analog, PHY, and interface IP.
Provide technical leadership for engagement with external IP, design-service, and technology partners.
Drive designs from pre-silicon architecture and verification through tapeout, bring-up, characterization, post-silicon validation, and production.
Diagnose complex performance and integration issues across silicon, package, board, and system boundaries.
Provide technical leadership, design reviews, mentoring, and architectural guidance across the engineering organization.
Help establish the design flows, standards, and infrastructure needed to build a world-class AMS capability from the ground up.
Required Skills and Qualifications:
Master’s degree or Ph.D. in Electrical Engineering, Electronics Engineering, Microelectronics, or a related field, or equivalent practical experience.
Deep experience in analog and mixed-signal IC design and implementation.
Strong background in high-speed PHY architecture and design, such as DDR, HBM, die-to-die, UCIe, SerDes, MIPI, or similar interfaces.
Experience developing and integrating analog IP such as PLLs/DLLs, clocking circuits, voltage/reference circuits, ADCs/DACs, LDOs, IO, or related mixed-signal functions.
Strong understanding of SoC integration, including clocking, timing/STA, low-power design, UPF, IO integration, physical design interaction, and floorplanning.
Experience with high-speed signal integrity and power integrity across chip, package, and PCB.
Demonstrated ability to take complex silicon designs from architecture through tapeout and post-silicon validation.
Experience working closely with package, board, digital, verification, physical-design, and system engineering teams.
Strong technical judgment and the ability to independently drive ambiguous, cross-functional engineering problems.
Ability to influence architecture and technical direction without relying on organizational authority.
Desired Skills:
Direct experience with UCIe or proprietary die-to-die interfaces.
Experience with advanced packaging, chiplets, or multi-die systems.
Experience developing complete PHY subsystems from architecture through silicon validation.
Background in IO/ESD and latch-up design and qualification.
Experience with analog timing characterization and design-flow/CAD infrastructure.
Experience managing or technically leading third-party IP and design-service vendors.
Experience building new design teams, flows, or technical capabilities from the ground up.
Prior technical leadership or mentoring experience across AMS, PHY, DV, or SoC integration teams.
Compensation
Competitive compensation aligned with Taiwan senior engineering roles. Exact compensation will vary based on experience and location.
We are an equal opportunity employer. We value a range of perspectives and experiences and make employment decisions based on merit and business needs. We do not discriminate on the basis of legally protected characteristics.
Agency Note:
We do not accept resumes from agencies or search firms. Please do not forward candidate profiles through our careers page, email, LinkedIn messages, or directly to company employees. Any resumes submitted will be deemed the property of the company, and no fees will be paid in the event the candidate is hired.
","descriptionPlain":"Principal AMS Engineer - Taiwan\n\nWho we are:\n\nWe are a startup building foundational technology to address performance, scalability, and resiliency challenges in large-scale AI data center clusters. We are backed by top-tier VC firms and notable angel investors. \n \nThe company is led by experienced builders and operators who have founded companies, taken them to scale, and exited successfully. We work with a strong sense of unity and shared responsibility, and we expect trust, integrity, and respect in how we collaborate and make decisions. We hold ourselves accountable to one another and to the quality of the work we deliver. \n \nHeadquartered in Silicon Valley, we operate across a mix of remote and on-site locations in the U.S. and Canada. We aim to create an environment where people are treated fairly, supported in their growth, and are empowered to do meaningful work alongside others who take the craft seriously.\n\nWhat we need:\n\nWe are looking for a Principal AMS Engineer to help architect, design, integrate, and validate the high-speed analog and mixed-signal technologies at the core of our products.\n\nThis is a highly technical, hands-on role spanning AMS/PHY architecture, circuit design, SoC integration, high-speed interfaces, clocking, power, package and board interaction, and silicon validation. You will work across the full development lifecycle—from early architecture and IP definition through implementation, tapeout, bring-up, and mass production.\n\nThe right person is comfortable operating beyond an individual circuit block. You understand how PHY, analog, digital, package, PCB, power, timing, and system-level considerations interact and can drive solutions across those boundaries.\n\nKey Responsibilities:\n\n - Architect and develop analog and mixed-signal circuits and subsystems for next-generation high-speed interfaces and SoCs.\n\n - Lead architecture and integration of high-speed PHY technologies, including die-to-die, UCIe-class interfaces, DDR, HBM, and related SerDes/PHY functions.\n\n - Guide development of critical AMS functions including clocking, reference circuits, DLL/PLL-related functions, voltage monitoring, calibration, data-path circuitry, and other custom analog IP.\n\n - Drive chip/package/PCB co-design for high-speed signal and power integrity.\n\n - Own AMS for PHY integration into complex SoCs, including interface definition, floorplanning, clocking, timing, power intent, IO, and physical implementation considerations.\n\n - Partner closely with digital design, verification, physical design, package, systems, and software teams to resolve cross-domain design issues.\n\n - Develop and improve methodologies for signal integrity, power integrity, timing, low-power design, and system-level analysis.\n\n - Define requirements and evaluate internal and third-party analog, PHY, and interface IP.\n\n - Provide technical leadership for engagement with external IP, design-service, and technology partners.\n\n - Drive designs from pre-silicon architecture and verification through tapeout, bring-up, characterization, post-silicon validation, and production.\n\n - Diagnose complex performance and integration issues across silicon, package, board, and system boundaries.\n\n - Provide technical leadership, design reviews, mentoring, and architectural guidance across the engineering organization.\n\n - Help establish the design flows, standards, and infrastructure needed to build a world-class AMS capability from the ground up.\n\nRequired Skills and Qualifications:\n\n - Master’s degree or Ph.D. in Electrical Engineering, Electronics Engineering, Microelectronics, or a related field, or equivalent practical experience.\n\n - Deep experience in analog and mixed-signal IC design and implementation.\n\n - Strong background in high-speed PHY architecture and design, such as DDR, HBM, die-to-die, UCIe, SerDes, MIPI, or similar interfaces.\n\n - Experience developing and integrating analog IP such as PLLs/DLLs, clocking circuits, voltage/reference circuits, ADCs/DACs, LDOs, IO, or related mixed-signal functions.\n\n - Strong understanding of SoC integration, including clocking, timing/STA, low-power design, UPF, IO integration, physical design interaction, and floorplanning.\n\n - Experience with high-speed signal integrity and power integrity across chip, package, and PCB.\n\n - Demonstrated ability to take complex silicon designs from architecture through tapeout and post-silicon validation.\n\n - Experience working closely with package, board, digital, verification, physical-design, and system engineering teams.\n\n - Strong technical judgment and the ability to independently drive ambiguous, cross-functional engineering problems.\n\n - Ability to influence architecture and technical direction without relying on organizational authority.\n\nDesired Skills:\n\n - Direct experience with UCIe or proprietary die-to-die interfaces.\n\n - Experience with advanced packaging, chiplets, or multi-die systems.\n\n - Experience developing complete PHY subsystems from architecture through silicon validation.\n\n - Background in IO/ESD and latch-up design and qualification.\n\n - Experience with analog timing characterization and design-flow/CAD infrastructure.\n\n - Experience managing or technically leading third-party IP and design-service vendors.\n\n - Experience building new design teams, flows, or technical capabilities from the ground up.\n\n - Prior technical leadership or mentoring experience across AMS, PHY, DV, or SoC integration teams.\n\nCompensation\n\nCompetitive compensation aligned with Taiwan senior engineering roles. Exact compensation will vary based on experience and location.\n\nWe are an equal opportunity employer. We value a range of perspectives and experiences and make employment decisions based on merit and business needs. We do not discriminate on the basis of legally protected characteristics.\n\n \n\nAgency Note:\n\nWe do not accept resumes from agencies or search firms. Please do not forward candidate profiles through our careers page, email, LinkedIn messages, or directly to company employees. Any resumes submitted will be deemed the property of the company, and no fees will be paid in the event the candidate is hired.\n\n\n\n"},{"id":"3fa180fd-3ddf-4073-9a5f-1f051b189030","title":"Software Development Engineer in Test - AI","department":"Software","team":"Software","employmentType":"FullTime","location":"Palo Alto","secondaryLocations":[],"publishedAt":"2026-08-31T17:31:05.716+00:00","isListed":true,"isRemote":true,"workplaceType":"Hybrid","address":{"postalAddress":{"postalCode":"94306","addressRegion":"California","streetAddress":"2175 Park Blvd","addressCountry":"United States","addressLocality":"Palo Alto"}},"jobUrl":"https://jobs.ashbyhq.com/delos-data/3fa180fd-3ddf-4073-9a5f-1f051b189030","applyUrl":"https://jobs.ashbyhq.com/delos-data/3fa180fd-3ddf-4073-9a5f-1f051b189030/application","descriptionHtml":"Software Development Engineer in Test - AI
About us:
We are a startup building foundational technology to address performance, scalability, and resiliency challenges in large-scale AI data center clusters. We are backed by top-tier VC firms and notable angel investors.
The company is led by experienced builders and operators who have founded companies, taken them to scale, and exited successfully. We work with a strong sense of unity and shared responsibility, and we expect trust, integrity, and respect in how we collaborate and make decisions. We hold ourselves accountable to one another and to the quality of the work we deliver.
Headquartered in Silicon Valley, we operate across a mix of remote and on-site locations in the U.S. and Canada. We aim to create an environment where people are treated fairly, supported in their growth, and are empowered to do meaningful work alongside others who take the craft seriously.
Some Recent Press: https://www.eetimes.com/startup-boosts-scale-up-to-1000-gpus-in-a-single-domain/
We are looking for:
We are looking for a Software Development Engineer in Test (SDET) to ensure the reliability and performance of our core AI infrastructure. In this role, you are an engineer who builds sophisticated automation frameworks and stress-testing suites to break and then harden our system.
You will be responsible for validating the intersection of distributed systems, GPU kernels, and AI frameworks. You will build a scalable foundation of trust in our code, ensuring that our performance-critical primitives work every time, at any scale.
Key Responsibilities:
Design, develop, and maintain a robust automated testing framework from the ground up that supports distributed AI training and inference workloads.
Develop complex test plans that go beyond unit tests, focusing on end-to-end system integration, stress testing, and hardware-software boundary conditions.
Partner closely with System Engineers to debug deep-seated issues in distributed clusters, using telemetry and profiling tools to identify bottlenecks.
Required Skills and Qualifications:
Strong proficiency in Python (for automation and orchestration).
Proven experience building or extending test automation frameworks for complex back-end systems.
Proven ability to troubleshoot automated test failures within complex large-scale distributed systems, and identify root causes.
Experience with containerization (Docker/Kubernetes) and modern CI/CD tools (GitHub Actions, GitLab CI, or Jenkins).
Desired Skills:
Experience with Kubernetes or Terraform or Ansible for managing test-bed environments.
Experience testing high-performance networking protocols or distributed file systems.
Experience testing software that interacts directly with drivers or firmware.
Education:
Bachelor's or Master's degree in Computer Engineering, Computer Science, or a related field.
Location:
This is a hybrid role based in Palo Alto.
Compensation:
Target base salary for this role is $140,000 - $220,000 per year + meaningful equity + benefits + 401k. Our salary ranges are determined by role, level, experience, and location.
We are an equal opportunity employer. We value a range of perspectives and experiences and make employment decisions based on merit and business needs. We do not discriminate on the basis of legally protected characteristics.
Agency Note:
We do not accept resumes from agencies or search firms. Please do not forward candidate profiles through our careers page, email, LinkedIn messages, or directly to company employees. Any resumes submitted will be deemed the property of the company, and no fees will be paid in the event the candidate is hired.
#LI-EW1
","descriptionPlain":"Software Development Engineer in Test - AI\n\n \n\nAbout us:\n\nWe are a startup building foundational technology to address performance, scalability, and resiliency challenges in large-scale AI data center clusters. We are backed by top-tier VC firms and notable angel investors.\n\nThe company is led by experienced builders and operators who have founded companies, taken them to scale, and exited successfully. We work with a strong sense of unity and shared responsibility, and we expect trust, integrity, and respect in how we collaborate and make decisions. We hold ourselves accountable to one another and to the quality of the work we deliver.\n\nHeadquartered in Silicon Valley, we operate across a mix of remote and on-site locations in the U.S. and Canada. We aim to create an environment where people are treated fairly, supported in their growth, and are empowered to do meaningful work alongside others who take the craft seriously.\n\nSome Recent Press: https://www.eetimes.com/startup-boosts-scale-up-to-1000-gpus-in-a-single-domain/\n\nWe are looking for:\n\nWe are looking for a Software Development Engineer in Test (SDET) to ensure the reliability and performance of our core AI infrastructure. In this role, you are an engineer who builds sophisticated automation frameworks and stress-testing suites to break and then harden our system.\n\nYou will be responsible for validating the intersection of distributed systems, GPU kernels, and AI frameworks. You will build a scalable foundation of trust in our code, ensuring that our performance-critical primitives work every time, at any scale.\n\n \n\nKey Responsibilities:\n\n - Design, develop, and maintain a robust automated testing framework from the ground up that supports distributed AI training and inference workloads.\n\n - Develop complex test plans that go beyond unit tests, focusing on end-to-end system integration, stress testing, and hardware-software boundary conditions.\n\n - Partner closely with System Engineers to debug deep-seated issues in distributed clusters, using telemetry and profiling tools to identify bottlenecks.\n \n \n\nRequired Skills and Qualifications:\n\n - Strong proficiency in Python (for automation and orchestration).\n\n - Proven experience building or extending test automation frameworks for complex back-end systems.\n\n - Proven ability to troubleshoot automated test failures within complex large-scale distributed systems, and identify root causes.\n\n - Experience with containerization (Docker/Kubernetes) and modern CI/CD tools (GitHub Actions, GitLab CI, or Jenkins).\n \n \n\nDesired Skills:\n\n - Experience with Kubernetes or Terraform or Ansible for managing test-bed environments.\n\n - Experience testing high-performance networking protocols or distributed file systems.\n\n - Experience testing software that interacts directly with drivers or firmware.\n \n \n\nEducation:\n\n - Bachelor's or Master's degree in Computer Engineering, Computer Science, or a related field.\n\nLocation:\n\nThis is a hybrid role based in Palo Alto.\n\nCompensation:\n\nTarget base salary for this role is $140,000 - $220,000 per year + meaningful equity + benefits + 401k. Our salary ranges are determined by role, level, experience, and location.\n\nWe are an equal opportunity employer. We value a range of perspectives and experiences and make employment decisions based on merit and business needs. We do not discriminate on the basis of legally protected characteristics.\n\nAgency Note:\n\nWe do not accept resumes from agencies or search firms. Please do not forward candidate profiles through our careers page, email, LinkedIn messages, or directly to company employees. Any resumes submitted will be deemed the property of the company, and no fees will be paid in the event the candidate is hired.\n\n#LI-EW1"},{"id":"d0ea09a0-8335-4f4c-addb-a75ca23cc0b8","title":"SerDes Validation Leader","department":"Systems","team":"Systems","employmentType":"FullTime","location":"Palo Alto","secondaryLocations":[],"publishedAt":"2026-09-14T20:56:58.794+00:00","isListed":true,"isRemote":true,"workplaceType":"Remote","address":{"postalAddress":{"postalCode":"94306","addressRegion":"California","streetAddress":"2175 Park Blvd","addressCountry":"United States","addressLocality":"Palo Alto"}},"jobUrl":"https://jobs.ashbyhq.com/delos-data/d0ea09a0-8335-4f4c-addb-a75ca23cc0b8","applyUrl":"https://jobs.ashbyhq.com/delos-data/d0ea09a0-8335-4f4c-addb-a75ca23cc0b8/application","descriptionHtml":"SerDes Validation Lead
Who we are
We are a startup building foundational technology to address performance, scalability, and resiliency challenges in large-scale AI data center clusters. We are backed by top-tier VC firms and notable angel investors.
The company is led by experienced builders and operators who have founded companies, taken them to scale, and exited successfully. We work with a strong sense of unity and shared responsibility, and we expect trust, integrity, and respect in how we collaborate and make decisions. We hold ourselves accountable to one another and to the quality of the work we deliver.
Headquartered in Silicon Valley, we operate across a mix of remote and on-site locations in the U.S. and Canada. We aim to create an environment where people are treated fairly, supported in their growth, and empowered to do meaningful work alongside others who take the craft seriously.
About the role
We are seeking a SerDes Implementation Lead to own the physical-layer implementation, configuration, tuning, and post-silicon validation of ultra-high-speed data links, including 112G and 224G PAM4.
This is a hands-on technical role for someone who has taken SerDes IP macros from integration through bring-up, tuned equalization parameters in real systems, and driven links to stable operation across challenging physical channels. You will work closely with signal integrity, power integrity, hardware, and firmware teams to correlate real-world channel behavior with transceiver settings and system-level performance.
What you’ll do
Drive implementation and register-level configuration of high-speed SerDes IP blocks across custom hardware systems.
Own transceiver equalization tuning, including CTLE, FFE, and DFE tap optimization, to maximize eye margin and minimize bit error rates across cable, backplane, and board-level topologies.
Lead post-silicon physical-layer bring-up, characterization, and debugging of 112G and 224G PAM4 links.
Use high-bandwidth oscilloscopes, BERTs, pattern generators, and protocol analyzers to validate link performance and isolate issues.
Collaborate closely with SI/PI engineers to correlate lab-measured link behavior with layout, simulation, and channel models.
Work with firmware teams to support real-time link monitoring, configuration control, and automated validation flows.
Develop and run script-based lab automation, including Python-based test, measurement, and characterization workflows.
Help define best practices for SerDes bring-up, tuning, debug, and validation across the company’s hardware platforms.
What we’re looking for
Proven hands-on experience bringing up and validating physical 56G, 112G, or 224G PAM4 links, or high-speed PCIe Gen5/Gen6 interfaces.
Deep practical understanding of SerDes implementation, configuration, equalization, and physical-layer debug.
Strong knowledge of how TX/RX equalization settings affect signal integrity, jitter profiles, eye margin, and BER.
Advanced proficiency with high-speed lab equipment, including BERTs, real-time or sampling oscilloscopes, pattern generators, and protocol analyzers.
Experience with automated, script-based testing and lab characterization, preferably using Python.
Ability to debug complex link issues across silicon, board, cable, backplane, firmware, and system-level interactions.
Strong collaboration skills and the ability to work closely with SI/PI, hardware, firmware, and systems teams in a fast-moving engineering environment.
Nice to have
Experience with 112G or 224G PAM4 links in data center, networking, switch, accelerator, or high-performance compute environments.
Familiarity with Ethernet, PCIe, CXL, or other high-speed protocols.
Experience working with SerDes IP from major commercial IP providers or custom in-house SerDes teams.
Exposure to channel modeling, compliance testing, and production validation flows.
Compensation:
Target base salary for this role is $180,000 – $260,000 per year, plus meaningful equity, benefits, and 401(k). Salary ranges are determined by role, level, experience, and location.
We are an equal opportunity employer. We value a range of perspectives and experiences and make employment decisions based on merit and business needs. We do not discriminate on the basis of legally protected characteristics.
Agency Note:
We do not accept resumes from agencies or search firms. Please do not forward candidate profiles through our careers page, email, LinkedIn messages, or directly to company employees. Any resumes submitted will be deemed the property of the company, and no fees will be paid in the event the candidate is hired.
","descriptionPlain":"SerDes Validation Lead\n\nWho we are\n\nWe are a startup building foundational technology to address performance, scalability, and resiliency challenges in large-scale AI data center clusters. We are backed by top-tier VC firms and notable angel investors.\n\nThe company is led by experienced builders and operators who have founded companies, taken them to scale, and exited successfully. We work with a strong sense of unity and shared responsibility, and we expect trust, integrity, and respect in how we collaborate and make decisions. We hold ourselves accountable to one another and to the quality of the work we deliver.\n\nHeadquartered in Silicon Valley, we operate across a mix of remote and on-site locations in the U.S. and Canada. We aim to create an environment where people are treated fairly, supported in their growth, and empowered to do meaningful work alongside others who take the craft seriously.\n\nAbout the role\n\nWe are seeking a SerDes Implementation Lead to own the physical-layer implementation, configuration, tuning, and post-silicon validation of ultra-high-speed data links, including 112G and 224G PAM4.\n\nThis is a hands-on technical role for someone who has taken SerDes IP macros from integration through bring-up, tuned equalization parameters in real systems, and driven links to stable operation across challenging physical channels. You will work closely with signal integrity, power integrity, hardware, and firmware teams to correlate real-world channel behavior with transceiver settings and system-level performance.\n\nWhat you’ll do\n\n - Drive implementation and register-level configuration of high-speed SerDes IP blocks across custom hardware systems.\n\n - Own transceiver equalization tuning, including CTLE, FFE, and DFE tap optimization, to maximize eye margin and minimize bit error rates across cable, backplane, and board-level topologies.\n\n - Lead post-silicon physical-layer bring-up, characterization, and debugging of 112G and 224G PAM4 links.\n\n - Use high-bandwidth oscilloscopes, BERTs, pattern generators, and protocol analyzers to validate link performance and isolate issues.\n\n - Collaborate closely with SI/PI engineers to correlate lab-measured link behavior with layout, simulation, and channel models.\n\n - Work with firmware teams to support real-time link monitoring, configuration control, and automated validation flows.\n\n - Develop and run script-based lab automation, including Python-based test, measurement, and characterization workflows.\n\n - Help define best practices for SerDes bring-up, tuning, debug, and validation across the company’s hardware platforms.\n\nWhat we’re looking for\n\n - Proven hands-on experience bringing up and validating physical 56G, 112G, or 224G PAM4 links, or high-speed PCIe Gen5/Gen6 interfaces.\n\n - Deep practical understanding of SerDes implementation, configuration, equalization, and physical-layer debug.\n\n - Strong knowledge of how TX/RX equalization settings affect signal integrity, jitter profiles, eye margin, and BER.\n\n - Advanced proficiency with high-speed lab equipment, including BERTs, real-time or sampling oscilloscopes, pattern generators, and protocol analyzers.\n\n - Experience with automated, script-based testing and lab characterization, preferably using Python.\n\n - Ability to debug complex link issues across silicon, board, cable, backplane, firmware, and system-level interactions.\n\n - Strong collaboration skills and the ability to work closely with SI/PI, hardware, firmware, and systems teams in a fast-moving engineering environment.\n\nNice to have\n\n - Experience with 112G or 224G PAM4 links in data center, networking, switch, accelerator, or high-performance compute environments.\n\n - Familiarity with Ethernet, PCIe, CXL, or other high-speed protocols.\n\n - Experience working with SerDes IP from major commercial IP providers or custom in-house SerDes teams.\n\n - Exposure to channel modeling, compliance testing, and production validation flows.\n \n \n\nCompensation:\n\nTarget base salary for this role is $180,000 – $260,000 per year, plus meaningful equity, benefits, and 401(k). Salary ranges are determined by role, level, experience, and location.\n\nWe are an equal opportunity employer. We value a range of perspectives and experiences and make employment decisions based on merit and business needs. We do not discriminate on the basis of legally protected characteristics.\n\nAgency Note:\n\nWe do not accept resumes from agencies or search firms. Please do not forward candidate profiles through our careers page, email, LinkedIn messages, or directly to company employees. Any resumes submitted will be deemed the property of the company, and no fees will be paid in the event the candidate is hired.\n\n"},{"id":"b954d6d7-a27d-4669-be97-5070190345d8","title":"Physical Design Engineer","department":"Hardware","team":"Hardware","employmentType":"FullTime","location":"Palo Alto","secondaryLocations":[],"publishedAt":"2026-09-10T21:32:04.769+00:00","isListed":true,"isRemote":true,"workplaceType":"Remote","address":{"postalAddress":{"postalCode":"94306","addressRegion":"California","streetAddress":"2175 Park Blvd","addressCountry":"United States","addressLocality":"Palo Alto"}},"jobUrl":"https://jobs.ashbyhq.com/delos-data/b954d6d7-a27d-4669-be97-5070190345d8","applyUrl":"https://jobs.ashbyhq.com/delos-data/b954d6d7-a27d-4669-be97-5070190345d8/application","descriptionHtml":"We are a startup building foundational technology to address performance, scalability, and resiliency challenges in large-scale AI data center clusters. We are backed by top-tier VC firms and notable angel investors.
The company is led by experienced builders and operators who have founded companies, taken them to scale, and exited successfully. We work with a strong sense of unity and shared responsibility, and we expect trust, integrity, and respect in how we collaborate and make decisions. We hold ourselves accountable to one another and to the quality of the work we deliver.
Headquartered in Silicon Valley, we operate across a mix of remote and on-site locations in the U.S. and Canada. We aim to create an environment where people are treated fairly, supported in their growth, and are empowered to do meaningful work alongside others who take the craft seriously.
What We Need:
We are looking for a Principal Physical Design Engineer to serve as an early member of our physical design team.
You will own some of the most challenging physical implementation problems in the design, drive critical blocks and top-level integration, and help establish the methodologies required to achieve performance, power, area, and schedule targets.
This is a deeply hands-on role for an engineer who can independently take complex designs from floorplan through signoff, solve difficult timing and implementation problems, and provide technical leadership across the broader physical design team.
Key Responsibilities:
Own physical implementation of complex blocks and subsystems from synthesized netlist through signoff.
Develop floorplans considering hierarchy, macros, interfaces, congestion, timing, power, and routability.
Develop and optimize power-grid implementations and support IR-drop and electromigration closure.
Drive placement, optimization, clock-tree synthesis, routing, extraction, timing closure, and ECO implementation.
Own difficult setup, hold, signal-integrity, congestion, and physical implementation problems.
Lead timing closure across block boundaries and support top-level timing convergence.
Perform and drive static timing analysis across multiple modes and corners.
Support signal-integrity analysis and timing impact from crosstalk, variation, and physical effects.
Drive physical signoff, including DRC, LVS, antenna, density, connectivity, and related physical verification requirements.
Perform or support power integrity analysis, including static and dynamic IR drop and electromigration.
Develop implementation strategies for high-performance and physically challenging portions of the design.
Partner with RTL and architecture teams to identify implementation problems early and recommend architectural or logical changes where appropriate.
Work closely with DFT, verification, package, SI/PI, and other engineering teams to resolve cross-functional design issues.
Develop and improve physical design flows, scripts, automation, metrics, and methodologies.
Evaluate implementation results and identify opportunities to improve PPA, runtime, convergence, and design quality.
Provide technical guidance and mentorship to other physical design engineers.
Participate in design reviews, methodology reviews, and tapeout readiness assessments.
Serve as a technical escalation point for complex physical design and signoff issues.
Required Skills and Qualifications:
10+ years of ASIC or SoC physical design experience with multiple successful tapeouts.
Expert-level understanding of floorplanning, placement, CTS, routing, optimization, timing closure, ECOs, and physical verification.
Strong expertise in static timing analysis and multi-mode, multi-corner timing closure.
Strong understanding of power delivery, IR drop, electromigration, and signal integrity.
Demonstrated ability to independently own complex blocks or major portions of a chip through signoff.
Strong understanding of clock design, timing constraints, variation, extraction, and advanced-node physical effects.
Experience with industry-standard Cadence and/or Synopsys physical implementation and signoff tools.
Strong scripting and automation skills using Tcl, Python, Perl, or similar languages.
Ability to debug complex design problems across RTL, timing, physical implementation, and signoff domains.
Strong communication skills and ability to provide technical leadership without requiring formal management authority.
Desired Skills:
Experience with advanced process nodes.
Experience with large, high-frequency or highly interconnected semiconductor designs.
Experience with hierarchical design and top-level physical integration.
Experience developing physical design methodologies and automation.
Experience working closely with package, SI/PI, and power-delivery teams.
Experience with multi-die, chiplet, or advanced packaging architectures.
Familiarity with EDA tool evaluation, benchmarking, and optimization.
Experience in an early-stage semiconductor environment.
Additional Requirements:
Ability to independently drive complex technical problems to closure.
Comfortable operating across both detailed implementation work and broader chip-level design considerations.
Ability to work effectively in a highly collaborative, fast-paced engineering organization.
Compensation:
Target base salary for this role is $180,000 – $260,000 per year, plus meaningful equity, benefits, and 401(k). Salary ranges are determined by role, level, experience, and location.
We are an equal opportunity employer. We value a range of perspectives and experiences and make employment decisions based on merit and business needs. We do not discriminate on the basis of legally protected characteristics.
Agency Note:
We do not accept resumes from agencies or search firms. Please do not forward candidate profiles through our careers page, email, LinkedIn messages, or directly to company employees. Any resumes submitted will be deemed the property of the company, and no fees will be paid in the event the candidate is hired.
#LI-EW1
Forward Deployed Engineer - AI
About us
We are a startup building foundational technology to address performance, scalability, and resiliency challenges in large-scale AI data center clusters. We are backed by top-tier VC firms and notable angel investors.
The company is led by experienced builders and operators who have founded companies, taken them to scale, and exited successfully. We work with a strong sense of unity and shared responsibility, and we expect trust, integrity, and respect in how we collaborate and make decisions. We hold ourselves accountable to one another and to the quality of the work we deliver.
Headquartered in Silicon Valley, we operate across a mix of remote and on-site locations in the U.S., Canada, and the U.K. We aim to create an environment where people are treated fairly, supported in their growth, and are empowered to do meaningful work alongside others who take the craft seriously.
Some Recent Press:
We are looking for:
We are looking for a talented Forward Deployed Engineer to be embedded with one of our strategic customers running our software in production. In this role, you will work hands-on inside the customer's AI data center environment, solving hard deployment and operational problems and turning what you learn into new product features alongside our engineering team. While most of your time will go to this customer, you will also bring your field experience to future customer pursuits, contributing hands-on to RFPs, technical evaluations, and new deployments. We are looking for a \"builder\" who has built and run AI infrastructure at scale, ideally at a neocloud or frontier AI lab, and who thrives on solving real problems in production.
Key Responsibilities
Serve as the dedicated technical owner for a strategic customer's production deployment of our software.
Work hands-on in the customer's AI data center environment, including GPU/XPU clusters, high-speed fabrics, schedulers, and orchestration layers.
Lead integration, troubleshooting, performance tuning, and root-cause analysis for production issues.
Guide the customer through software upgrades, cluster expansion, and new feature rollouts.
Build runbooks, integration guides, and automation tailored to the customer's environment.
Build deep working relationships with the customer's infrastructure, SRE, and platform engineering teams.
Turn customer problems into clear technical requirements and work with our engineering team to design and deliver new features.
Write and test code (Python, Bash, APIs) to prototype fixes, integrations, and tooling in the field.
Feed structured insights on bugs, feature gaps, and competitive needs back into product and engineering, and align customer milestones with our product release cycles.
Contribute hands-on technical work to RFPs, RFIs, technical evaluations, and proof-of-concept deployments for new customers.
Help build reference architectures, demo environments, and technical collateral, and represent the company at customer briefings, technical workshops, and industry events as needed.
Required Skills and Qualifications
5+ years in a hands-on infrastructure engineering role (forward deployed engineer, SRE, platform engineer, solutions architect, or similar) with direct customer or internal-customer exposure.
Proven AI data center experience: deploying and operating GPU/XPU clusters with high-speed interconnects (InfiniBand/RoCE/Ethernet/NVLink), job scheduling, and training/inference workloads.
Strong software problem-solving skills, including debugging complex distributed systems and writing production-quality scripts and tools in Python and Bash.
Hands-on experience with AI infrastructure software such as Kubernetes, Slurm, Tinkerbell, Canonical MaaS, observability stacks, or infrastructure management platforms.
Deep proficiency with Linux, containers, and APIs.
Track record of working with engineering teams to define and ship features based on field needs.
Clear communicator, comfortable whiteboarding with SREs and briefing senior infrastructure leaders.
Willingness to work on-site with the customer and travel as needed.
Desired Skills
Experience as a forward deployed or embedded engineer dedicated to a single large customer.
Experience taking early-stage or pre-launch products into hyperscale, neocloud, or AI lab environments.
Familiarity with inference serving and performance optimization (e.g., KV-cache behavior, disaggregated serving, GPU utilization analysis).
Background with observability stacks (Prometheus, Grafana, OpenTelemetry) and data pipelines for infrastructure analytics.
Prior experience at an AI infrastructure software vendor, GPU cloud provider, networking vendor, or hyperscaler.
Education
Bachelor's or Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or a related field, or equivalent practical experience.
Location
This role is on-site at customer’s office based in Cambridge, UK.
Compensation
Target base salary for this role is £115k–£135k per year + equity. Our salary ranges are determined by role, level, experience, and location.
We are an equal opportunity employer. We value a range of perspectives and experiences and make employment decisions based on merit and business needs. We do not discriminate on the basis of legally protected characteristics.
Agency Note:
We do not accept resumes from agencies or search firms. Please do not forward candidate profiles through our careers page, email, LinkedIn messages, or directly to company employees. Any resumes submitted will be deemed the property of the company, and no fees will be paid in the event the candidate is hired.
#LI-EW1
","descriptionPlain":"Forward Deployed Engineer - AI\n\nAbout us\n\nWe are a startup building foundational technology to address performance, scalability, and resiliency challenges in large-scale AI data center clusters. We are backed by top-tier VC firms and notable angel investors.\n\nThe company is led by experienced builders and operators who have founded companies, taken them to scale, and exited successfully. We work with a strong sense of unity and shared responsibility, and we expect trust, integrity, and respect in how we collaborate and make decisions. We hold ourselves accountable to one another and to the quality of the work we deliver.\n\nHeadquartered in Silicon Valley, we operate across a mix of remote and on-site locations in the U.S., Canada, and the U.K. We aim to create an environment where people are treated fairly, supported in their growth, and are empowered to do meaningful work alongside others who take the craft seriously.\n\nSome Recent Press:\n\nhttps://www.reuters.com/business/delos-data-chip-startup-founded-by-intel-veterans-raises-100-million-ai-networks-2026-09-15/\n\nWe are looking for:\n\nWe are looking for a talented Forward Deployed Engineer to be embedded with one of our strategic customers running our software in production. In this role, you will work hands-on inside the customer's AI data center environment, solving hard deployment and operational problems and turning what you learn into new product features alongside our engineering team. While most of your time will go to this customer, you will also bring your field experience to future customer pursuits, contributing hands-on to RFPs, technical evaluations, and new deployments. We are looking for a \"builder\" who has built and run AI infrastructure at scale, ideally at a neocloud or frontier AI lab, and who thrives on solving real problems in production.\n\nKey Responsibilities\n\n - Serve as the dedicated technical owner for a strategic customer's production deployment of our software.\n\n - Work hands-on in the customer's AI data center environment, including GPU/XPU clusters, high-speed fabrics, schedulers, and orchestration layers.\n\n - Lead integration, troubleshooting, performance tuning, and root-cause analysis for production issues.\n\n - Guide the customer through software upgrades, cluster expansion, and new feature rollouts.\n\n - Build runbooks, integration guides, and automation tailored to the customer's environment.\n\n - Build deep working relationships with the customer's infrastructure, SRE, and platform engineering teams.\n\n - Turn customer problems into clear technical requirements and work with our engineering team to design and deliver new features.\n\n - Write and test code (Python, Bash, APIs) to prototype fixes, integrations, and tooling in the field.\n\n - Feed structured insights on bugs, feature gaps, and competitive needs back into product and engineering, and align customer milestones with our product release cycles.\n\n - Contribute hands-on technical work to RFPs, RFIs, technical evaluations, and proof-of-concept deployments for new customers.\n\n - Help build reference architectures, demo environments, and technical collateral, and represent the company at customer briefings, technical workshops, and industry events as needed.\n\nRequired Skills and Qualifications\n\n - 5+ years in a hands-on infrastructure engineering role (forward deployed engineer, SRE, platform engineer, solutions architect, or similar) with direct customer or internal-customer exposure.\n\n - Proven AI data center experience: deploying and operating GPU/XPU clusters with high-speed interconnects (InfiniBand/RoCE/Ethernet/NVLink), job scheduling, and training/inference workloads.\n\n - Strong software problem-solving skills, including debugging complex distributed systems and writing production-quality scripts and tools in Python and Bash.\n\n - Hands-on experience with AI infrastructure software such as Kubernetes, Slurm, Tinkerbell, Canonical MaaS, observability stacks, or infrastructure management platforms.\n\n - Deep proficiency with Linux, containers, and APIs.\n\n - Track record of working with engineering teams to define and ship features based on field needs.\n\n - Clear communicator, comfortable whiteboarding with SREs and briefing senior infrastructure leaders.\n\n - Willingness to work on-site with the customer and travel as needed.\n\nDesired Skills\n\n - Experience as a forward deployed or embedded engineer dedicated to a single large customer.\n\n - Experience taking early-stage or pre-launch products into hyperscale, neocloud, or AI lab environments.\n\n - Familiarity with inference serving and performance optimization (e.g., KV-cache behavior, disaggregated serving, GPU utilization analysis).\n\n - Background with observability stacks (Prometheus, Grafana, OpenTelemetry) and data pipelines for infrastructure analytics.\n\n - Prior experience at an AI infrastructure software vendor, GPU cloud provider, networking vendor, or hyperscaler.\n\nEducation\n\n - Bachelor's or Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or a related field, or equivalent practical experience.\n\nLocation\n\nThis role is on-site at customer’s office based in Cambridge, UK.\n\nCompensation\n\nTarget base salary for this role is £115k–£135k per year + equity. Our salary ranges are determined by role, level, experience, and location.\n\nWe are an equal opportunity employer. We value a range of perspectives and experiences and make employment decisions based on merit and business needs. We do not discriminate on the basis of legally protected characteristics.\n\nAgency Note:\n\nWe do not accept resumes from agencies or search firms. Please do not forward candidate profiles through our careers page, email, LinkedIn messages, or directly to company employees. Any resumes submitted will be deemed the property of the company, and no fees will be paid in the event the candidate is hired.\n\n#LI-EW1\n\n\n\n"},{"id":"5e69c121-9909-4c52-a81c-030a0f0234dc","title":"Principal Package Engineer","department":"Systems","team":"Systems","employmentType":"FullTime","location":"Palo Alto","secondaryLocations":[],"publishedAt":"2026-10-01T20:05:37.824+00:00","isListed":true,"isRemote":true,"workplaceType":"Hybrid","address":{"postalAddress":{"postalCode":"94306","addressRegion":"California","streetAddress":"2175 Park Blvd","addressCountry":"United States","addressLocality":"Palo Alto"}},"jobUrl":"https://jobs.ashbyhq.com/delos-data/5e69c121-9909-4c52-a81c-030a0f0234dc","applyUrl":"https://jobs.ashbyhq.com/delos-data/5e69c121-9909-4c52-a81c-030a0f0234dc/application","descriptionHtml":"Who We Are
We are a startup building foundational technology to address performance, scalability, and resiliency challenges in large‑scale AI data center clusters. We are backed by top‑tier VC firms and notable angel investors. The company is led by experienced builders and operators who have founded companies, taken them to scale, and exited successfully. We work with a strong sense of unity and shared responsibility, and we expect trust, integrity, and respect in how we collaborate and make decisions. We hold ourselves accountable to one another and to the quality of the work we deliver. Headquartered in Silicon Valley, we operate across a mix of remote and on‑site locations in the U.S. and Canada. We aim to create an environment where people are treated fairly, supported in their growth, and are empowered to do meaningful work alongside others who take the craft seriously.
Some Recent Press: https://www.eetimes.com/startup-boosts-scale-up-to-1000-gpus-in-a-single-domain/
What We Need
A Senior Packaging Engineer responsible for architecting and delivering advanced multi‑die IC packages for high‑performance AI accelerators. This role focuses on package architecture, substrate design, manufacturability, and vendor engagement.
Key Responsibilities
Select and design optimal multi‑die package types (MCM, 2.5D, 3D, fan‑out, CoWoS, InFO, CPC, CPO) balancing electrical performance, thermal behavior, cost, and manufacturability.
Define package specifications, bump map and ball map, interposer requirements, and mechanical constraints.
Define substrate stack‑ups, bump pitch, ball pitch, routing, via structures, and material choices for performance and manufacturability.
Perform high-speed signal escaping, routing and power distribution network design.
Manage subcontractors and work directly with TSMC and/or OSAT on bumping, substrate options, and advanced packaging flows.
Partner with IC design, physical design, SI/PI, and board teams to ensure package requirements meet system‑level needs.
Evaluate emerging packaging technologies and drive adoption for next‑generation products.
Support package‑level bring‑up, failure analysis, debug and qualification.
Required Skills & Qualifications
B.S./M.S. in Electrical Engineering or related field.
Experience with multi‑die package design and UCIe (AP/SP) integration.
Understanding of substrate materials, stack‑ups, and mechanical constraints.
Familiarity with SI/PI concepts to collaborate effectively with electrical teams.
Experience managing packaging subcontractors.
Experience interfacing with TSMC/OSAT for bumping and packaging options.
Knowledge of package modeling tools (HFSS, Sigrity, or similar) is a plus.
Compensation
Target base salary for this role is $180,000–$270,000 per year + meaningful equity + benefits + 401k. Our salary ranges are determined by role, level, experience, and location.
We are an equal opportunity employer. We value a range of perspectives and experiences and make employment decisions based on merit and business needs. We do not discriminate on the basis of legally protected characteristics.
Agency Note:
We do not accept resumes from agencies or search firms. Please do not forward candidate profiles through our careers page, email, LinkedIn messages, or directly to company employees. Any resumes submitted will be deemed the property of the company, and no fees will be paid in the event the candidate is hired.
#LI-EW1
","descriptionPlain":"Who We Are\n\nWe are a startup building foundational technology to address performance, scalability, and resiliency challenges in large‑scale AI data center clusters. We are backed by top‑tier VC firms and notable angel investors. The company is led by experienced builders and operators who have founded companies, taken them to scale, and exited successfully. We work with a strong sense of unity and shared responsibility, and we expect trust, integrity, and respect in how we collaborate and make decisions. We hold ourselves accountable to one another and to the quality of the work we deliver. Headquartered in Silicon Valley, we operate across a mix of remote and on‑site locations in the U.S. and Canada. We aim to create an environment where people are treated fairly, supported in their growth, and are empowered to do meaningful work alongside others who take the craft seriously.\n\nSome Recent Press: https://www.eetimes.com/startup-boosts-scale-up-to-1000-gpus-in-a-single-domain/\n\nWhat We Need\n\nA Senior Packaging Engineer responsible for architecting and delivering advanced multi‑die IC packages for high‑performance AI accelerators. This role focuses on package architecture, substrate design, manufacturability, and vendor engagement.\n\nKey Responsibilities\n\n - Select and design optimal multi‑die package types (MCM, 2.5D, 3D, fan‑out, CoWoS, InFO, CPC, CPO) balancing electrical performance, thermal behavior, cost, and manufacturability.\n\n - Define package specifications, bump map and ball map, interposer requirements, and mechanical constraints.\n\n - Define substrate stack‑ups, bump pitch, ball pitch, routing, via structures, and material choices for performance and manufacturability.\n\n - Perform high-speed signal escaping, routing and power distribution network design.\n\n - Manage subcontractors and work directly with TSMC and/or OSAT on bumping, substrate options, and advanced packaging flows.\n\n - Partner with IC design, physical design, SI/PI, and board teams to ensure package requirements meet system‑level needs.\n\n - Evaluate emerging packaging technologies and drive adoption for next‑generation products.\n\n - Support package‑level bring‑up, failure analysis, debug and qualification.\n\nRequired Skills & Qualifications\n\n - B.S./M.S. in Electrical Engineering or related field.\n\n - Experience with multi‑die package design and UCIe (AP/SP) integration.\n\n - Understanding of substrate materials, stack‑ups, and mechanical constraints.\n\n - Familiarity with SI/PI concepts to collaborate effectively with electrical teams.\n\n - Experience managing packaging subcontractors.\n\n - Experience interfacing with TSMC/OSAT for bumping and packaging options.\n\n - Knowledge of package modeling tools (HFSS, Sigrity, or similar) is a plus.\n\nCompensation\n\nTarget base salary for this role is $180,000–$270,000 per year + meaningful equity + benefits + 401k. Our salary ranges are determined by role, level, experience, and location.\n\nWe are an equal opportunity employer. We value a range of perspectives and experiences and make employment decisions based on merit and business needs. We do not discriminate on the basis of legally protected characteristics.\n\nAgency Note:\n\nWe do not accept resumes from agencies or search firms. Please do not forward candidate profiles through our careers page, email, LinkedIn messages, or directly to company employees. Any resumes submitted will be deemed the property of the company, and no fees will be paid in the event the candidate is hired.\n\n#LI-EW1"},{"id":"d2bf7cf1-382e-4073-935a-6c8037d37448","title":"DFT Engineer","department":"Hardware","team":"Hardware","employmentType":"FullTime","location":"Palo Alto","secondaryLocations":[],"publishedAt":"2026-09-23T18:36:38.840+00:00","isListed":true,"isRemote":true,"workplaceType":"Remote","address":{"postalAddress":{"postalCode":"94306","addressRegion":"California","streetAddress":"2175 Park Blvd","addressCountry":"United States","addressLocality":"Palo Alto"}},"jobUrl":"https://jobs.ashbyhq.com/delos-data/d2bf7cf1-382e-4073-935a-6c8037d37448","applyUrl":"https://jobs.ashbyhq.com/delos-data/d2bf7cf1-382e-4073-935a-6c8037d37448/application","descriptionHtml":"DFT Engineer - Verification
Who we are:
We are a startup building foundational technology to address performance, scalability, and resiliency challenges in large-scale AI data center clusters. We are backed by top-tier VC firms and notable angel investors.
The company is led by experienced builders and operators who have founded companies, taken them to scale, and exited successfully. We work with a strong sense of unity and shared responsibility, and we expect trust, integrity, and respect in how we collaborate and make decisions. We hold ourselves accountable to one another and to the quality of the work we deliver.
Headquartered in Silicon Valley, we operate across a mix of remote and on-site locations in the U.S. and Canada. We aim to create an environment where people are treated fairly, supported in their growth, and are empowered to do meaningful work alongside others who take the craft seriously.
Some Recent Press: https://www.eetimes.com/startup-boosts-scale-up-to-1000-gpus-in-a-single-domain/
What we need:
A Senior DFT Verification Engineer responsible for ensuring the functionality, correctness, and quality of ASIC DFT logic. This role focuses on building robust verification environments, executing coverage-driven verification plans, and working closely with DFT design engineers and manufacturing engineers to deliver reliable, high-quality silicon.
The ideal candidate has deep hands-on experience with SystemVerilog, UVM (or similar methodologies), and modern verification workflows, and is comfortable driving verification efforts from planning through closure. The ideal candidate is also knowledgeable about DFT topics such as scan/ATPG, JTAG, ijtag (ICL/PDL), boundary scan, MBIST, memory repair, and fuseboxes. Should have experience with gate-level simulation and tester pattern formats such as STIL.
Key Responsibilities:
Develop, implement, and maintain RTL verification environments using UVM or equivalent methodologies
Create and execute coverage-driven verification plans aligned with design specifications
Use EDA DFT tools (e.g., TestMax, Tessent) to create and run recommended pre-silicon test cases for MBIST and scan fabric inserted by those tools
Develop directed test cases for other (non-vendor-supplied) DFT logic to validate functionality and identify corner cases
Assist in verifying ATPG patterns, especially at SOC level, along with manufacturing reset sequences
Analyze simulation results, debug complex verification and design issues, and perform root-cause analysis in collaboration with DFT design engineers
Implement and track functional and code coverage, driving verification to closure
Develop reusable verification components and write SystemVerilog Assertions (SVA)
Participate in design and verification reviews, providing input on design testability, correctness, and optimization
Automate regression testing and enhance verification infrastructure using Python and scripting
Contribute to continuous improvement of verification processes, tools, and methodologies
Along with the DFT designers, help support post-silicon test bring-up debug
Required Skills and Qualifications:
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
5+ years of experience in digital design verification, with at least 2 in DFT verification specifically
Strong hands-on experience with UVM-based or similar verification methodologies
Proficiency in SystemVerilog
Experience in scripting (preferably Python) and automation
Experience with industry-standard EDA tools (e.g., Synopsys VCS, Siemens/Mentor Questa, Cadence Xcelium)
Experience with industry-standard EDA DFT tools (e.g., Synopsys TestMax + Yield Accelerator, Siemens Tessent)
Solid understanding of digital design fundamentals
Experience with verification of test sequences for high-speed PHY logic including PCIe and Ethernet (10G/40G/100G)
Strong analytical and problem-solving skills
Clear written and verbal communication skills for cross-functional collaboration
High attention to detail and ability to deliver reliable, high-quality verification outcomes
Ability to work independently and manage tasks to completion
Desired Skills:
Experience with change control systems, especially git
Experience verifying SoC-level designs
Compensation:
Target base salary for this role is $180,000 – $260,000 per year, plus meaningful equity, benefits, and 401(k). Salary ranges are determined by role, level, experience, and location.
We are an equal opportunity employer. We value a range of perspectives and experiences and make employment decisions based on merit and business needs. We do not discriminate on the basis of legally protected characteristics.
Agency Note:
We do not accept resumes from agencies or search firms. Please do not forward candidate profiles through our careers page, email, LinkedIn messages, or directly to company employees. Any resumes submitted will be deemed the property of the company, and no fees will be paid in the event the candidate is hired.
#LI-EW1
","descriptionPlain":"DFT Engineer - Verification \n\n\n\nWho we are:\n\nWe are a startup building foundational technology to address performance, scalability, and resiliency challenges in large-scale AI data center clusters. We are backed by top-tier VC firms and notable angel investors.\n\nThe company is led by experienced builders and operators who have founded companies, taken them to scale, and exited successfully. We work with a strong sense of unity and shared responsibility, and we expect trust, integrity, and respect in how we collaborate and make decisions. We hold ourselves accountable to one another and to the quality of the work we deliver.\n\nHeadquartered in Silicon Valley, we operate across a mix of remote and on-site locations in the U.S. and Canada. We aim to create an environment where people are treated fairly, supported in their growth, and are empowered to do meaningful work alongside others who take the craft seriously.\n\nSome Recent Press: https://www.eetimes.com/startup-boosts-scale-up-to-1000-gpus-in-a-single-domain/\n\nWhat we need:\n\nA Senior DFT Verification Engineer responsible for ensuring the functionality, correctness, and quality of ASIC DFT logic. This role focuses on building robust verification environments, executing coverage-driven verification plans, and working closely with DFT design engineers and manufacturing engineers to deliver reliable, high-quality silicon.\n\nThe ideal candidate has deep hands-on experience with SystemVerilog, UVM (or similar methodologies), and modern verification workflows, and is comfortable driving verification efforts from planning through closure. The ideal candidate is also knowledgeable about DFT topics such as scan/ATPG, JTAG, ijtag (ICL/PDL), boundary scan, MBIST, memory repair, and fuseboxes. Should have experience with gate-level simulation and tester pattern formats such as STIL.\n\n\n\nKey Responsibilities:\n\n - Develop, implement, and maintain RTL verification environments using UVM or equivalent methodologies\n\n - Create and execute coverage-driven verification plans aligned with design specifications\n\n - Use EDA DFT tools (e.g., TestMax, Tessent) to create and run recommended pre-silicon test cases for MBIST and scan fabric inserted by those tools\n\n - Develop directed test cases for other (non-vendor-supplied) DFT logic to validate functionality and identify corner cases\n\n - Assist in verifying ATPG patterns, especially at SOC level, along with manufacturing reset sequences\n\n - Analyze simulation results, debug complex verification and design issues, and perform root-cause analysis in collaboration with DFT design engineers\n\n - Implement and track functional and code coverage, driving verification to closure\n\n - Develop reusable verification components and write SystemVerilog Assertions (SVA)\n\n - Participate in design and verification reviews, providing input on design testability, correctness, and optimization\n\n - Automate regression testing and enhance verification infrastructure using Python and scripting\n\n - Contribute to continuous improvement of verification processes, tools, and methodologies\n\n - Along with the DFT designers, help support post-silicon test bring-up debug\n\n\n\nRequired Skills and Qualifications:\n\n - Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field\n\n - 5+ years of experience in digital design verification, with at least 2 in DFT verification specifically\n\n - Strong hands-on experience with UVM-based or similar verification methodologies\n\n - Proficiency in SystemVerilog\n\n - Experience in scripting (preferably Python) and automation\n\n - Experience with industry-standard EDA tools (e.g., Synopsys VCS, Siemens/Mentor Questa, Cadence Xcelium)\n\n - Experience with industry-standard EDA DFT tools (e.g., Synopsys TestMax + Yield Accelerator, Siemens Tessent)\n\n - Solid understanding of digital design fundamentals\n\n - Experience with verification of test sequences for high-speed PHY logic including PCIe and Ethernet (10G/40G/100G)\n\n - Strong analytical and problem-solving skills\n\n - Clear written and verbal communication skills for cross-functional collaboration\n\n - High attention to detail and ability to deliver reliable, high-quality verification outcomes\n\n - Ability to work independently and manage tasks to completion\n\n\n\nDesired Skills:\n\n - Experience with change control systems, especially git\n\n - Experience verifying SoC-level designs\n\n\n\nCompensation:\n\nTarget base salary for this role is $180,000 – $260,000 per year, plus meaningful equity, benefits, and 401(k). Salary ranges are determined by role, level, experience, and location.\n\nWe are an equal opportunity employer. We value a range of perspectives and experiences and make employment decisions based on merit and business needs. We do not discriminate on the basis of legally protected characteristics.\n\nAgency Note:\n\nWe do not accept resumes from agencies or search firms. Please do not forward candidate profiles through our careers page, email, LinkedIn messages, or directly to company employees. Any resumes submitted will be deemed the property of the company, and no fees will be paid in the event the candidate is hired.\n\n#LI-EW1"},{"id":"e6efdc4d-8b6e-4477-a94a-65d783ddae71","title":"Senior Electrical Engineer, Server Hardware 資深伺服器硬體工程師","department":"Systems","team":"Systems","employmentType":"FullTime","location":"Taiwan","secondaryLocations":[],"publishedAt":"2026-10-01T20:53:56.874+00:00","isListed":true,"isRemote":true,"workplaceType":"Remote","address":{"postalAddress":{"addressRegion":"Taiwan","addressCountry":"Taiwan","addressLocality":"Hsinchu"}},"jobUrl":"https://jobs.ashbyhq.com/delos-data/e6efdc4d-8b6e-4477-a94a-65d783ddae71","applyUrl":"https://jobs.ashbyhq.com/delos-data/e6efdc4d-8b6e-4477-a94a-65d783ddae71/application","descriptionHtml":"Senior Electrical Engineer – Board & System Design (Taiwan) Taipei or Hsinchu
Who We Are
We are a startup building foundational technology to address performance, scalability, and resiliency challenges in large‑scale AI data center clusters. We are backed by top‑tier VC firms and notable angel investors. The company is led by experienced builders and operators who have founded companies, taken them to scale, and exited successfully. We work with a strong sense of unity and shared responsibility, and we expect trust, integrity, and respect in how we collaborate and make decisions. We hold ourselves accountable to one another and to the quality of the work we deliver. Headquartered in Silicon Valley, we operate across a mix of remote and on‑site locations in the U.S., Canada, and Taiwan. We aim to create an environment where people are treated fairly, supported in their growth, and empowered to do meaningful work alongside others who take the craft seriously.
What We Need
We are seeking a Senior Electrical Engineer based in Taiwan with deep experience in board‑level design, system architecture, and server/data‑center hardware development. This role will drive board design execution, system integration, and technical engagement with ODMs and customers to deliver high‑performance compute platforms.
Key Responsibilities
Board Architecture & Design — Lead schematic design, component selection, and power‑tree definition for complex server and data‑center boards.
System‑Level Design — Define system architecture, high‑speed interface requirements, power delivery strategy, and thermal/mechanical constraints.
Data Center & Server Hardware — Develop boards and systems supporting CPUs, accelerators, memory subsystems, high‑speed IO, and advanced power architectures.
ODM Engagement — Work closely with Taiwan ODMs on design reviews, issue resolution, schedule alignment, and manufacturing readiness.
Customer Interaction — Support customer technical discussions, requirements gathering, and design‑in activities.
High‑Speed Interfaces — Collaborate with SI/PI teams to ensure compliance for PCIe, CXL, Ethernet, UCIe, CPO, and other high‑speed links.
Validation & Bring‑Up — Lead board bring‑up, debug, and system‑level validation using scopes, logic analyzers, and protocol analyzers.
Cross‑Functional Collaboration — Partner with packaging, SI/PI, firmware, and mechanical teams to deliver fully integrated systems.
Manufacturing Support — Drive DFM/DFT reviews, support factory builds, and resolve production issues with ODM partners.
Required Skills & Qualifications
B.S./M.S. in Electrical Engineering or related field.
8+ years of experience in board design and system‑level hardware development.
Strong background in server, data‑center, or high‑performance compute platforms.
Expertise in schematic capture, power architecture, and high‑speed digital design.
Experience working directly with Taiwan ODMs (Quanta, Wistron, Inventec, Foxconn, etc.).
Familiarity with PCIe, CXL, DDR, Ethernet, CPO, and other high‑speed interfaces.
Hands‑on experience with lab equipment (oscilloscopes, logic analyzers, protocol analyzers).
Ability to lead cross‑functional technical discussions with customers and partners.
Knowledge of SI/PI fundamentals is a plus.
Experience with server‑class power delivery (VRMs, multiphase regulators) is a plus.
Compensation
Competitive compensation aligned with Taiwan senior engineering roles. Exact compensation will vary based on experience and location.
We are an equal opportunity employer. We value a range of perspectives and experiences and make employment decisions based on merit and business needs. We do not discriminate on the basis of legally protected characteristics.
Agency Note:
We do not accept resumes from agencies or search firms. Please do not forward candidate profiles through our careers page, email, LinkedIn messages, or directly to company employees. Any resumes submitted will be deemed the property of the company, and no fees will be paid in the event the candidate is hired.
#LI-EW1
","descriptionPlain":"Senior Electrical Engineer – Board & System Design (Taiwan) Taipei or Hsinchu\n\n\n\nWho We Are\n\nWe are a startup building foundational technology to address performance, scalability, and resiliency challenges in large‑scale AI data center clusters. We are backed by top‑tier VC firms and notable angel investors. The company is led by experienced builders and operators who have founded companies, taken them to scale, and exited successfully. We work with a strong sense of unity and shared responsibility, and we expect trust, integrity, and respect in how we collaborate and make decisions. We hold ourselves accountable to one another and to the quality of the work we deliver. Headquartered in Silicon Valley, we operate across a mix of remote and on‑site locations in the U.S., Canada, and Taiwan. We aim to create an environment where people are treated fairly, supported in their growth, and empowered to do meaningful work alongside others who take the craft seriously.\n\n\n\nWhat We Need\n\nWe are seeking a Senior Electrical Engineer based in Taiwan with deep experience in board‑level design, system architecture, and server/data‑center hardware development. This role will drive board design execution, system integration, and technical engagement with ODMs and customers to deliver high‑performance compute platforms.\n\n\n\nKey Responsibilities\n\n - Board Architecture & Design — Lead schematic design, component selection, and power‑tree definition for complex server and data‑center boards.\n\n - System‑Level Design — Define system architecture, high‑speed interface requirements, power delivery strategy, and thermal/mechanical constraints.\n\n - Data Center & Server Hardware — Develop boards and systems supporting CPUs, accelerators, memory subsystems, high‑speed IO, and advanced power architectures.\n\n - ODM Engagement — Work closely with Taiwan ODMs on design reviews, issue resolution, schedule alignment, and manufacturing readiness.\n\n - Customer Interaction — Support customer technical discussions, requirements gathering, and design‑in activities.\n\n - High‑Speed Interfaces — Collaborate with SI/PI teams to ensure compliance for PCIe, CXL, Ethernet, UCIe, CPO, and other high‑speed links.\n\n - Validation & Bring‑Up — Lead board bring‑up, debug, and system‑level validation using scopes, logic analyzers, and protocol analyzers.\n\n - Cross‑Functional Collaboration — Partner with packaging, SI/PI, firmware, and mechanical teams to deliver fully integrated systems.\n\n - Manufacturing Support — Drive DFM/DFT reviews, support factory builds, and resolve production issues with ODM partners.\n \n \n\nRequired Skills & Qualifications\n\n - B.S./M.S. in Electrical Engineering or related field.\n\n - 8+ years of experience in board design and system‑level hardware development.\n\n - Strong background in server, data‑center, or high‑performance compute platforms.\n\n - Expertise in schematic capture, power architecture, and high‑speed digital design.\n\n - Experience working directly with Taiwan ODMs (Quanta, Wistron, Inventec, Foxconn, etc.).\n\n - Familiarity with PCIe, CXL, DDR, Ethernet, CPO, and other high‑speed interfaces.\n\n - Hands‑on experience with lab equipment (oscilloscopes, logic analyzers, protocol analyzers).\n\n - Ability to lead cross‑functional technical discussions with customers and partners.\n\n - Knowledge of SI/PI fundamentals is a plus.\n\n - Experience with server‑class power delivery (VRMs, multiphase regulators) is a plus.\n \n \n\nCompensation\n\nCompetitive compensation aligned with Taiwan senior engineering roles. Exact compensation will vary based on experience and location.\n\nWe are an equal opportunity employer. We value a range of perspectives and experiences and make employment decisions based on merit and business needs. We do not discriminate on the basis of legally protected characteristics.\n\n\n\nAgency Note:\n\nWe do not accept resumes from agencies or search firms. Please do not forward candidate profiles through our careers page, email, LinkedIn messages, or directly to company employees. Any resumes submitted will be deemed the property of the company, and no fees will be paid in the event the candidate is hired.\n\n#LI-EW1"}],"apiVersion":"1"}